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arxiv: 2202.08244 · v2 · submitted 2022-02-16 · 🪐 quant-ph · physics.app-ph· physics.atom-ph

Industrially Microfabricated Ion Trap with 1 eV Trap Depth

S. Auchter , C. Axline , C. Decaroli , M. Valentini , L. Purwin , R. Oswald , R. Matt , E. Aschauer
show 7 more authors
Y. Colombe P. Holz T. Monz R. Blatt P. Schindler C. R\"ossler J. Home
This is my paper

Pith reviewed 2026-05-24 12:03 UTC · model grok-4.3

classification 🪐 quant-ph physics.app-phphysics.atom-ph
keywords ion trapmicrofabricationMEMStrapped ionstrap depthquantum computingcalcium ionwafer bonding
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The pith

Stacked 8-inch wafers produce 3D ion traps with 1 eV depth via MEMS fabrication.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper demonstrates a fabrication method that stacks two electrode-patterned 8-inch wafers with a spacer to form symmetric three-dimensional ion traps. This yields a trap depth of 1 eV for calcium-40 ions positioned 200 micrometers from the electrode planes while maintaining 2.5 micrometer alignment precision across the stack. The approach addresses the need for scalable, reproducible traps in quantum computing by leveraging industrial MEMS processes instead of custom fabrication. Experimental characterization confirms mode frequencies agree with simulations to within 5 percent and reports motional heating rates as low as 40 phonons per second at 1 MHz.

Core claim

An ion trap fabricated on stacked 8-inch wafers in a large-scale MEMS microfabrication process forms a 3D electrode structure with electrodes patterned on opposing wafers bonded to a spacer. This design achieves a trap depth of 1 eV for a calcium-40 ion held at 200 micrometers from either electrode plane, with 2.5 micrometer standard deviation in alignment across the stack. The traps are characterized with mode frequencies spanning 0.6 to 3.8 MHz agreeing with simulations to within plus or minus 5 percent, stray electric fields evaluated across sites, and motional heating rates measured over ranges of trap frequencies and temperatures.

What carries the argument

The stacked wafer 3D electrode configuration with bonded opposing electrode planes, which generates symmetric trapping potentials at high depth.

If this is right

  • Reproducible 3D traps can be produced at large volume using standard industrial processes.
  • Mode frequencies between 0.6 and 3.8 MHz match simulations to within 5 percent.
  • Stray electric fields can be evaluated and managed across multiple trapping sites.
  • Motional heating rates as low as 40 phonons per second occur at 1 MHz and 185 K.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The wafer-stacking method could support electrode patterns for multi-zone or segmented traps in a single device.
  • Similar industrial processes might extend to other ion species or larger trap arrays without custom machining.
  • High-volume production of such traps could lower barriers to building systems with hundreds of ions.

Load-bearing premise

The 2.5 micrometer standard deviation in wafer alignment across the stack does not cause significant degradation of the simulated 1 eV trap depth or introduce problematic stray fields.

What would settle it

A measured trap depth well below 1 eV or unexpectedly high stray fields at the ion position when the fabricated alignment deviation reaches 2.5 micrometers.

Figures

Figures reproduced from arXiv: 2202.08244 by C. Axline, C. Decaroli, C. R\"ossler, E. Aschauer, J. Home, L. Purwin, M. Valentini, P. Holz, P. Schindler, R. Blatt, R. Matt, R. Oswald, S. Auchter, T. Monz, Y. Colombe.

Figure 1
Figure 1. Figure 1: Trap concept. a) Exploded view showing the three wafers that form the ion trap. The bottom wafer includes metal DC and RF electrodes. The glass spacer defines a nominal distance of 400 µm between top and bottom electrodes. Voltages applied to electrodes on the top wafer can adjust the confining potential. Laser access is possible from all four sides of the trap, and a slit between the top electrodes enable… view at source ↗
Figure 2
Figure 2. Figure 2: Trap fabrication. a) Schematic, radial cross section, and layer stack of the bottom, spacer, and top wafers, which are structured individually. Top electrodes are electrically connected by wirebonding to a bond pad on the highly-doped silicon. The bottom wafer consists of three metal layers (orange), isolated by oxide (blue). Vias in the inter-metal oxide (imox) connect individual metal layers. Laser acces… view at source ↗
Figure 3
Figure 3. Figure 3: Measurement of motional mode frequencies. a) The traps are tested in a cryogenic apparatus. Laser beams (purple) used for cooling and detecting (397 nm), repumping (854 nm, 866 nm), and photoionizing calcium atoms (375 nm, 423 nm) are introduced across the trap surface at 45◦ to the trap axis and 90◦ to the applied magnetic field B. Qubit manipulation is done with an opposite-facing beam (red) at 729 nm. L… view at source ↗
Figure 4
Figure 4. Figure 4: Measurement of stray static electric field components Ex, Ey, and Ez along the trap axis x and over time. a) Bottom wafer geometry (gray) overlaid with the glass spacers (blue) labeled 1–4. In the text, we assess how well data match with models of various stray field sources, including the side facets of these spacers and dielectric between or on top of the electrodes, to explain measured fields. Arrows de… view at source ↗
Figure 5
Figure 5. Figure 5: Heating rates are measured for axial (blue circles) and radial modes (green, orange circles) as a function of mode frequency, radial mode rotation, and trap temperature. a) Axially confining DC voltages are varied to adjust axial mode frequency, while the RF power is varied to adjust radial mode frequencies, with mode rotation angle θ = 38◦ . When DC voltage sources are disconnected, lower radial rates (di… view at source ↗
read the original abstract

Scaling trapped-ion quantum computing will require robust trapping of at least hundreds of ions over long periods, while increasing the complexity and functionality of the trap itself. Symmetric 3D structures enable high trap depth, but microfabrication techniques are generally better suited to planar structures that produce less ideal conditions for trapping. We present an ion trap fabricated on stacked 8-inch wafers in a large-scale MEMS microfabrication process that provides reproducible traps at a large volume. Electrodes are patterned on the surfaces of two opposing wafers bonded to a spacer, forming a 3D structure with 2.5 micrometer standard deviation in alignment across the stack. We implement a design achieving a trap depth of 1 eV for a calcium-40 ion held at 200 micrometers from either electrode plane. We characterize traps, achieving measurement agreement with simulations to within +/-5% for mode frequencies spanning 0.6--3.8 MHz, and evaluate stray electric field across multiple trapping sites. We measure motional heating rates over an extensive range of trap frequencies, and temperatures, observing 40 phonons/s at 1 MHz and 185 K. This fabrication method provides a highly scalable approach for producing a new generation of 3D ion traps.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The manuscript reports fabrication of a symmetric 3D ion trap on stacked 8-inch wafers via a large-scale MEMS process, with 2.5 μm alignment std. dev. across the stack. It claims realization of a design with 1 eV trap depth for 40Ca+ at 200 μm from either electrode plane, reports measured trap frequencies agreeing with simulation to within ±5% over 0.6–3.8 MHz, stray-field evaluation at multiple sites, and motional heating rates (e.g., 40 phonons/s at 1 MHz and 185 K) over ranges of frequency and temperature.

Significance. If the 1 eV depth is experimentally realized under the reported alignment tolerance, the work establishes a scalable industrial route to high-depth 3D traps, addressing a key barrier to scaling trapped-ion systems. The extensive heating-rate dataset across trap frequencies and temperatures is a concrete strength that will be useful to the community independent of the depth claim.

major comments (2)
  1. [Abstract] Abstract: the headline claim of a realized 1 eV trap depth rests on the fabricated geometry matching the simulated ideal, yet only frequency agreement (±5 %) is reported; no direct experimental bound on depth (escape-rate measurement, RF-amplitude scaling to loss, or similar) or sensitivity analysis of depth versus ±2.5 μm electrode shifts is supplied.
  2. [Fabrication description paragraph] Fabrication description paragraph: the 2.5 μm alignment std. dev. is presented as enabling the 1 eV depth, but without a tolerance study quantifying depth degradation under the observed misalignment distribution, it is impossible to confirm that the simulated value survives fabrication.
minor comments (1)
  1. [Abstract] The abstract states both 'achieving a trap depth of 1 eV' and 'we implement a design achieving…'; the distinction between simulated design value and measured device performance should be clarified in the main text.

Simulated Author's Rebuttal

2 responses · 1 unresolved

We thank the referee for their careful review and for highlighting both the potential impact of the work and the areas needing clarification. We respond to each major comment below.

read point-by-point responses

  1. Referee: [Abstract] Abstract: the headline claim of a realized 1 eV trap depth rests on the fabricated geometry matching the simulated ideal, yet only frequency agreement (±5 %) is reported; no direct experimental bound on depth (escape-rate measurement, RF-amplitude scaling to loss, or similar) or sensitivity analysis of depth versus ±2.5 μm electrode shifts is supplied.

    Authors: The reported 1 eV depth is obtained from electrostatic simulation of the nominal electrode geometry. The ±5 % agreement between measured and simulated trap frequencies across 0.6–3.8 MHz supplies the primary experimental validation that the fabricated structure reproduces the design. No direct experimental determination of trap depth (e.g., escape-rate or RF-amplitude scaling) was performed. We will add a sensitivity analysis of trap depth versus electrode misalignment of order ±2.5 μm to the revised manuscript. revision: yes

  2. Referee: [Fabrication description paragraph] Fabrication description paragraph: the 2.5 μm alignment std. dev. is presented as enabling the 1 eV depth, but without a tolerance study quantifying depth degradation under the observed misalignment distribution, it is impossible to confirm that the simulated value survives fabrication.

    Authors: We agree that a quantitative tolerance study is required to substantiate the claim. The revised manuscript will include Monte-Carlo sampling of the measured 2.5 μm alignment distribution to show the resulting distribution of trap depths. revision: yes

standing simulated objections not resolved
  • Direct experimental bound on trap depth via escape-rate measurement, RF-amplitude scaling to loss, or equivalent method.

Circularity Check

0 steps flagged

No significant circularity; central claims rest on experimental measurements validated against independent simulations

full rationale

The paper's core results are direct experimental characterizations (mode frequencies agreeing with simulation to ±5%, stray fields, heating rates) of a fabricated device. The 1 eV trap depth is a design target obtained from electrostatic simulation of the nominal geometry; it is not derived from or fitted to the reported data. No equations reduce reported metrics to parameters defined by the same measurements, no load-bearing self-citations justify uniqueness or ansatzes, and the fabrication tolerances are stated as process outcomes rather than retrofitted to match performance. The derivation chain is therefore self-contained against external experimental benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The central claim rests on electromagnetic simulation accuracy for trap depth and on the assumption that MEMS alignment precision directly translates to the designed potential without unmodeled surface effects.

axioms (1)
  • domain assumption Standard electrostatic simulation of ion traps accurately predicts depth when electrode geometry is known to within fabrication tolerance.
    Invoked implicitly when stating that the design achieves 1 eV depth.

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Reference graph

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