Biorealistic response in a technology-compatible graphene synaptic transistor

Anastasia Chouprik; Elizaveta Guberna; Evgeny Guberna; Ilya Margolin; Islam Mutaev; Maxim Rybin

REVIEW 5 major objections 6 minor 18 references

Biorealistic response in a technology-compatible graphene synaptic transistor

T0 review · 5 major / 6 minor · reviewed 2026-08-10 · deepseek-v4-flash

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Pith's one-line read A graphene floating-gate transistor built from industry-compatible materials achieves nearly continuous conductance states and biorealistic synaptic timing, reproducing paired-pulse and spike-rate plasticity.

desk verdict Solid three-terminal graphene synapse with a genuinely useful split-Dirac-point design; the mechanism story needs controls, but the device work deserves peer review. read the letter →

arxiv 2501.05877 v1 pith:SI23SJA2 submitted 2025-01-10 physics.app-ph cond-mat.mes-hall

Anastasia Chouprik , Elizaveta Guberna , Islam Mutaev , Ilya Margolin , Evgeny Guberna , Maxim Rybin This is my paper · ORCID

classification physics.app-phcond-mat.mes-hall

keywords graphenesynaptictransistorfloating-gatememoryneuromorphichardwareplasticitypaired-pulsefacilitationspike-ratedependentshort-termCVD

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper sets out to show that a synaptic transistor can be made from industrially compatible materials—CVD graphene on an $\mathrm{HfO_2}$/TiN/$\mathrm{Al_2O_3}$ gate stack—and still behave like a biological synapse. The device stores charge gradually in a floating gate and in oxide-graphene interface traps, giving a virtually continuous set of conductance levels rather than discrete states. Its temporal relaxation after voltage pulses mirrors the short-term dynamics of real synapses, and it reproduces paired-pulse facilitation/depression, spike-rate-dependent plasticity, and the transition from short-term to long-term plasticity. The authors further show that device geometry and graphene surface state can be engineered to enlarge the memory window and shift the read point to zero gate voltage, reducing power consumption. If correct, this places a three-terminal, leak-resistant synapse within reach of standard semiconductor fabrication.

What carries the argument

The central object is a floating-gate field-effect transistor with a graphene conduction channel: a W back gate, $10\,\mathrm{nm}$ $\mathrm{HfO_2}$ blocking oxide, TiN floating gate, $5\,\mathrm{nm}$ $\mathrm{Al_2O_3}$ tunnel oxide, and CVD monolayer graphene, with the floating gate shorter than the channel so that only part of the channel is gated by it. That geometry splits the Dirac point into two features and widens the memory window, while the engineered asymmetry of the transfer curve places the largest memory window at $V_{\mathrm{READ}}=0$. The mechanism carrying the argument is the slow, gradual charging and discharging of the floating gate and of traps at the graphene/$\mathrm{Al_2O_3}$ interface: tunneling or thermionic emission transfers electrons into these reservoirs under a positive pulse and removes them under a negative pulse, so conductance relaxes on a timescale that mimics synaptic biochemistry.

What would settle it

Fabricate a control transistor identical except without the TiN floating gate, or with the floating gate electrically shorted to the back gate; if it still shows the same magnitude of hysteresis and the same pulse-rate-dependent relaxation, then floating-gate charge storage is not the cause. Alternatively, directly probe the floating-gate voltage with a high-impedance contact after a SET/RESET pulse and check that its change tracks the observed conductance relaxation on the same timescale.

Watch

Extended reading notes

Core claim

The central claim is that a three-terminal transistor with a graphene channel and a floating-gate stack exhibits a virtually continuous spectrum of conductance states whose time evolution is governed by gradual injection and emission of electrons into the floating gate and interface traps. This internal charge dynamics gives the device an intrinsic short-term memory that interacts with incoming spikes, so the final conductance depends on pulse amplitude, duration, rate, and history, not just on the last pulse. The paper reports memory windows of $4.2$ V for a $5\,\mu\mathrm{m}$ channel and $3.7$ V for a $10\,\mu\mathrm{m}$ channel, split Dirac points caused by the two differently gated channel regions, and the emulation of pulse-amplitude and pulse-duration dependent plasticity, paired-pulse facilitation/depression, spike-rate dependent plasticity, and the short-term to long-term plasticity transition. Because the read and write paths are separated by the gate electrode, the device avoids the sneak-path leakage that plagues two-terminal memristor arrays.

Load-bearing premise

The load-bearing premise is that the gradual conductance changes come from electrons being slowly injected into and released from the buried floating gate and oxide interface traps; the paper does not directly measure the charge on the floating gate or the trap population, so a different origin for the hysteresis—such as mobile ions, atmospheric adsorbates, or measurement artifacts—would undercut the claimed biorealistic mechanism.

Editorial extensions

If this is right

A three-terminal synapse built this way can be packed into crossbar-like arrays without the selector devices needed to suppress sneak paths in two-terminal memristor arrays, since the gate separates programming and readout.
The demonstrated memory window and near-continuous conductance levels make the device suitable for analog weight storage in hardware neural networks, with enough levels for multibit rather than binary weights.
Because the read voltage can be set to zero for the adsorbate-shifted devices, the same synaptic function can be obtained at lower power consumption than symmetric devices that must be biased during read.
The dependence of the final conductance on pulse amplitude, duration, and frequency means the same physical device can implement several plasticity rules, so a single array could support different learning protocols.
Encapsulation after preheating removes ambient adsorbates and yields stable, symmetric transfer curves, indicating the behavior is intrinsic to the charge-storage stack rather than to environmental doping.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

A direct test not reported in the paper: measuring the floating-gate potential with a high-impedance contact or Kelvin probe after SET/RESET pulses would confirm whether the conductance drift is indeed caused by stored electron charge rather than by mobile ions or adsorbate motion; the authors attribute the effect to electron injection and emission without directly measuring the charge state.
If the mechanism is as claimed, the tunnel oxide thickness and floating-gate length give two independent knobs to set the relaxation time constant, which could be tuned separately from the conductance range—a possible route to devices with programmable short-term memory timescales.
The observed asymmetry between positive and negative pulses implies that spike-timing-dependent plasticity protocols would need to be calibrated differently for potentiation and depression; this could be exploited by using one polarity for emulation and the other for reset, a design choice the paper mentions but does not elaborate.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Short take: this is a legitimate, well-executed device paper, and the split Dirac point design is the most interesting thing in it. Don't buy the mechanism story as proven, but the phenomenology looks real.

What's new: not the first graphene synapse or 2D floating-gate synapse, but the combination of CVD graphene, W/HfO2/TiN/Al2O3 stack, and a floating gate that covers only part of the channel gives a transfer curve with two Dirac points. That split lets them push the memory window close to graphene's room-temperature limit and, by keeping adsorbates, shift the window so reading happens at zero gate voltage. Those are concrete, useful engineering tricks. They then show the expected set of synaptic functions — PADP, PDDP, PPF/PPD, SRDP, STP-to-LTP — with clean-looking pulse measurements and a sensible story about relaxation between pulses and therefore frequency dependence.

What's soft: the device-to-device and run-to-run evidence is thin. No error bars, no endurance, no retention, no statistics across devices. The 'virtually continuous conductance levels' is supported by a family of I–V curves, but there's no count of distinct states or linearity check. More importantly, the paper attributes the dynamics to gradual electron injection/emission into the floating gate and interface traps. That's a plausible—indeed standard—model for this kind of stack, and the leakage currents and split Dirac points are consistent with it. But it remains an inference. No control device (e.g., same stack without a floating gate), no temperature or sweep-rate series, no direct charge measurement. High-k oxides can move ions and adsorbates could in principle contribute, so the mechanistic claim as stated ('the intrinsic mechanism is...') goes further than the evidence. The stress-test note is right on this, though I'd call it a soft spot rather than a fatal one: the device-level demonstrations don't depend on the exact trap/ion partition.

Citation pattern is fine, including the prior graphene memristive synapse and 2D floating-gate work. The paper doesn't oversell with respect to those; it claims incremental but solid engineering.

Who it's for: anyone working on three-terminal synaptic devices or graphene neuromorphic hardware. It deserves regular peer review, with requests for statistics and at least one control experiment before acceptance. I'd read the revised version.

Referee Report

5 major / 6 minor

Summary. The paper reports a three-terminal graphene floating-gate transistor, with a W/HfO2/TiN/Al2O3/graphene stack, and demonstrates several synaptic functions: pulse-amplitude and pulse-duration dependent plasticity, paired-pulse facilitation/depression, and spike-rate dependent plasticity. The authors attribute the device dynamics to gradual electron injection and emission into the floating gate and interface traps, and they show that shifting the Dirac point via controlled adsorbate doping allows reading at zero gate voltage. The central claim is that this technology-compatible device exhibits biorealistic, tunable plasticity with a virtually continuous range of conductance levels.

Significance. If the claims hold, the device is a useful addition to the synaptic-transistor landscape because it uses comparatively standard materials, a three-terminal architecture that avoids sneak-path problems, and direct experimental demonstration of several synaptic functions without reliance on fitted models. The zero-gate-voltage read scheme and the systematic comparison of two channel geometries are positive design contributions. However, the paper's significance is currently limited by the absence of device-to-device statistics, endurance and retention data, and direct verification of the proposed charge-trapping mechanism; the 'biorealistic' claim rests on qualitative analogy and on inferred, rather than directly measured, internal state dynamics.

major comments (5)

[Fig. 1(c) and the paragraph after Fig. 1(e)] The attribution of the conductance dynamics to gradual electron injection/emission into the floating gate and interface traps is inferred only from hysteresis, gate-leakage currents, and pulse-response relaxation. No control device without a floating gate, no temperature dependence, no sweep-rate dependence, and no direct measurement of the gate charge or trap population is provided. Because the abstract and the design-optimization claim explicitly rest on this mechanism, the authors should either add such control experiments or substantially temper the mechanistic language.
[Figs. 1(e) and 2 and the memory-window discussion] The paper states that 'Dirac point splitting causes the increase of the memory window,' yet the reported memory windows are 4.2 V for the 5-µm channel and 3.7 V for the 10-µm channel, while the 10-µm channel is described as having more prominent splitting. This apparent inconsistency needs an explanation, and the units of the memory-window values should be stated explicitly. Without this, the central design rule that geometry controls the memory window is not convincingly established.
[Figs. 2 and 3 and the conclusion] All electrical data appear to come from a single representative device or a single measurement; no error bars, no device-to-device variation, and no sample-size information are reported. Claims such as 'memory window reaches 4.2 and 3.7' and 'virtually continuous range of multiple conductance levels' require at least statistics over several devices, especially since the paper argues that the device geometry and interface state can be designed for optimized performance.
[Fig. 3 and the STP-LTP discussion] The introduction lists 'spike transition from short term plasticity (STP) to long term plasticity (LTP)' among the demonstrated functions, but the paper only shows relaxation to stationary values after single pulses and frequency-dependent responses. No experiment explicitly demonstrates a transition from short-term to long-term plasticity as a function of spike count or train duration. This claimed synaptic function is therefore not supported by the presented data.
[Fig. 3 and the conclusion] No endurance or retention data are presented, although the paper claims 'long-term memory' and describes the stationary conductance levels as stable. For a synaptic device intended for hardware neuromorphic systems, repeated write/erase cycling and retention over relevant timescales are essential. The absence of these data leaves the practicality claim unverified.

minor comments (6)

[Device fabrication paragraph] The phrase 'channel lengths were 5 and 10 µm2' contains a typo; the area unit should be removed, leaving '5 and 10 µm'.
[Memory-window paragraph after Fig. 1(e)] The memory-window values '4.2 and 3.7' are given without units; presumably they are in volts, and this should be stated.
[Paragraphs referring to Fig. 1(e)] The text refers to '[Fig. 1(d)]' when discussing transfer characteristics and the read voltage of -3 V; the intended reference appears to be Fig. 1(e).
[Fig. 1(e) and Fig. 2] The phrase 'not splitted' should be 'not split', and the notation for source-drain voltage should be consistent throughout (e.g., VSD rather than 'source-drain voltage equals to').
[Introduction and conclusion] The term 'all-technology-compatible' is not defined; the manuscript should specify which technology node or fabrication environment is meant, since CVD graphene transfer and e-beam evaporation are not standard CMOS front-end processes.
[Discussion of the memory-window limit] The statement that the memory window is 'close to its limit for graphene at room conditions' is unsupported by any reference or quantitative criterion; a citation or a definition of that limit is needed.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the paper is an experimental demonstration whose claims rest on direct device measurements, not on fitted parameters or self-referential definitions.

full rationale

The paper reports fabrication and electrical characterization of a graphene floating-gate synaptic transistor. The central claims—virtually continuous conductance levels, paired-pulse facilitation/depression, spike-rate-dependent plasticity, and the influence of device geometry on the memory window—are supported by measured transfer characteristics, pulse-response traces, and comparison of two device variants. There is no fitted model whose parameters are later repackaged as predictions, and no quantity is defined in terms of the outcome it is supposed to explain. The proposed mechanism (gradual electron injection/emission into the floating gate and interface traps) is an interpretation of the observed hysteresis and relaxation, consistent with the data but not required by any self-referential construction; the biological analogy is qualitative and does not feed back into the device parameters. No load-bearing self-citations are used: the only cited mechanism reference (Ref. 18, for oxide-trap hysteresis) is an external experimental study, not prior work by the same authors. The memory-window optimization is an empirical geometry/condition comparison, not a fitted prediction. Therefore the derivation chain is self-contained and the circularity score is 0.

Assumptions & free parameters 2 free parameters · 3 assumptions · 0 invented entities

The central claims rest on standard semiconductor physics and a plausible but unverified charge-trapping mechanism. There are no newly postulated physical entities, but the device operation relies on several domain assumptions. The read voltage and pulse amplitude ranges are hand-chosen operating parameters rather than fitted constants.

free parameters (2)

VREAD = 0 V = 0 V
Chosen by hand as the read voltage for the asymmetric transistor to minimize power consumption; the demonstration of synaptic functions depends on reading at this operating point.
SET/RESET pulse amplitude window = 4 to 7 V / -4 to -7 V
Selected to produce the continuous conductance range; these amplitudes are swept rather than fitted to a model, but they define the demonstrated operating envelope.

assumptions (3)

domain assumption Hysteresis and memory originate from charge trapping in the Al2O3/graphene interface and in the floating gate
The paper attributes the memory window to gradual electron injection and emission into these reservoirs, but does not directly measure the trapped charge. Invoked in the mechanism discussion after Fig. 1(e).
domain assumption The split Dirac point is caused by two distinct channel regions with different reservoir potentials
Used to explain the double-peak transfer characteristic and the enlarged memory window; this is a plausible but unverified model.
domain assumption Electrons cross the Al2O3 tunnel layer via tunneling or thermionic emission
Standard semiconductor device physics assumed for the injection mechanism during voltage pulses.

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Cite this review

Pith. "Pith review of Biorealistic response in a technology-compatible graphene synaptic transistor." pith.science (2026). https://pith.science/paper/SI23SJA2

@misc{pith2026250105877,
  author       = {Pith},
  title        = {Pith review of: Biorealistic response in a technology-compatible graphene synaptic transistor},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/SI23SJA2}},
  note         = {Machine review of arXiv:2501.05877}
}

read the original abstract

Artificial synapse is a key element of future brain-inspired neuromorphic computing systems implemented in hardware. This work presents a graphene synaptic transistor based on all-technology-compatible materials that exhibits highly tunable biorealistic behavior. It is shown that the device geometry and interface properties can be designed to maximize the memory window and minimize power consumption. The device exhibits a virtually continuous range of multiple conductance levels, similar to synaptic weighting, which is achieved by gradual injection/emission of electrons into the floating gate and interface traps under the influence of an external electric field. Similar to the biological synapse, the transistor has short-term intrinsic dynamics that affect the long-term state. The temporal injection/emission dynamics of an electronic synapse closely resemble those of its biological counterpart and is exploited to emulate biorealistic behavior using a number of synaptic functions, including paired-pulse facilitation/depression, spike-rate-dependent plasticity, and others. Such a synaptic transistor can serve as a building block in hardware artificial networks for advanced information processing and storage.

Figures

Figures reproduced from arXiv: 2501.05877 by the authors.

**Figure 1.** FIG. 1. Working principle of synaptic transistor with CVD graphene channel. (a) Scheme of the transistor structure. (b) [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗

**Figure 2.** FIG. 2. Memristive properties of transistors fabricated (a) [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗

**Figure 3.** FIG. 3. Synaptic functionality. (a) Pulse amplitude-dependent and (b) pulse duration-dependent plasticity. (c) Spike rate [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

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Pith tools

Reviewed August 10, 2026 · model on record in the stance chip above.

[1] [1]

author author S. H. \ Jo , author T. Chang , author I. Ebong , author B. B. \ Bhadviya , author P. Mazumder , \ and\ author W. Lu ,\ title title Nanoscale memristor device as synapse in neuromorphic systems , \ https://pubs.acs.org/doi/10.1021/nl904092h journal journal Nano Lett. \ volume 10 ,\ pages 1297--1301 ( year 2010 ) NoStop

doi:10.1021/nl904092h

[2] [2]

Yu , author Y

author author S. Yu , author Y. Wu , author R. Jeyasingh , author D. Kuzum , \ and\ author H. S. P. \ Wong ,\ title title An electronic synapse device based on metal oxide resistive switching memory for neuromorphic computation , \ https://doi.org/10.1109/TED.2011.2147791 journal journal IEEE Trans. Electron Devices \ volume 58 ,\ pages 2729--2737 ( year ...

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author author D. M. \ Kullmann , author D. J. \ Perkei , author T. Manabe , \ and\ author R. A. \ Nicoll ,\ title title Ca ^ 2+ entry via postsynaptic voltage-sensitive Ca ^ 2+ channels can transiently potentiate excitatory synaptic transmission in the hippocampus , \ https://doi.org/10.1016/0896-6273(92)90075-O journal journal Neuron \ volume 9 ,\ pages ...

work page doi:10.1016/0896-6273(92)90075-o

[4] [4]

Kim , author C

author author S. Kim , author C. Du , author P. Sheridan , author W. Ma , author S. Choi , \ and\ author W. D. \ Lu ,\ title title Experimental demonstration of a second-order memristor and its ability to biorealistically implement synaptic plasticity , \ https://doi.org/10.1021/acs.nanolett.5b00697 journal journal Nano Lett. \ volume 15 ,\ pages 2203--22...

work page doi:10.1021/acs.nanolett.5b00697

[5] [5]

Du , author W

author author C. Du , author W. Ma , author T. Chang , author P. Sheridan , \ and\ author W. D. \ Lu. ,\ title title Biorealistic implementation of synaptic functions with oxide memristors through internal ionic dynamics , \ https://doi.org/10.1002/adfm.201501427 journal journal Adv. Funct. Mater. \ volume 25 ,\ pages 4290--4299 ( year 2015 ) NoStop

work page doi:10.1002/adfm.201501427

[6] [6]

Wang , author S

author author Z. Wang , author S. Joshi , author S. E. \ Savel’ev , author H. Jiang , author R. Midya , author P. Lin , author M. Hu , author N. Ge , author J. P. \ Strachan , author Z. Li , author Q. Wu , author M. Barnell , author G.-L. \ Li , author H. L. \ Xin , author R. S. \ Williams , author Q. Xia , \ and\ author J. J. \ Yang ,\ title title Memris...

doi:10.1038/nmat4756

[7] [7]

Mikheev , author A

author author V. Mikheev , author A. Chouprik , author Y. Lebedinskii , author S. Zarubin , author Y. Matveyev , author E. Kondratyuk , author M. G. \ Kozodaev , author A. M. \ Markeev , author A. Zenkevich , \ and\ author D. Negrov ,\ title title Ferroelectric second-order memristor , \ https://doi.org/10.1021/acsami.9b08189 journal journal ACS Appl. Mat...

work page doi:10.1021/acsami.9b08189

[8] [8]

author author E. J. \ Fuller , author S. T. \ Keene , author A. Melianas , author Z. Wang , author S. Agarwal , author Y. Li , \ and\ author et al. ,\ title title Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing , \ https://doi.org/10.1126/science.aaw5581 journal journal Science \ volume 364 ,\ pages 570--574...

work page doi:10.1126/science.aaw5581