REVIEW 3 cited by
NeuroCoreX: An Open-Source FPGA-Based Spiking Neural Network Emulator with On-Chip Learning
Not yet reviewed by Pith; the record is open.
This paper has not been read by Pith yet. Machine review is queued; the pith claim, tier, and objections will appear here once it completes.
SPECIMEN: schema-true, not a live event
T0 review · schema-true
One-sentence machine reading of the paper's core claim.
pith:XXXXXXXX · record.json · timestamp
NeuroCoreX: An Open-Source FPGA-Based Spiking Neural Network Emulator with On-Chip Learning
read the original abstract
Spiking Neural Networks (SNNs) are computational models inspired by the structure and dynamics of biological neuronal networks. Their event-driven nature enables them to achieve high energy efficiency, particularly when deployed on neuromorphic hardware platforms. Unlike conventional Artificial Neural Networks (ANNs), which primarily rely on layered architectures, SNNs naturally support a wide range of connectivity patterns, from traditional layered structures to small-world graphs characterized by locally dense and globally sparse connections. In this work, we introduce NeuroCoreX, an FPGA-based emulator designed for the flexible co-design and testing of SNNs. NeuroCoreX supports all-to-all connectivity, providing the capability to implement diverse network topologies without architectural restrictions. It features a biologically motivated local learning mechanism based on Spike-Timing-Dependent Plasticity (STDP). The neuron model implemented within NeuroCoreX is the Leaky Integrate-and-Fire (LIF) model, with current-based synapses facilitating spike integration and transmission . A Universal Asynchronous Receiver-Transmitter (UART) interface is provided for programming and configuring the network parameters, including neuron, synapse, and learning rule settings. Users interact with the emulator through a simple Python-based interface, streamlining SNN deployment from model design to hardware execution. NeuroCoreX is released as an open-source framework, aiming to accelerate research and development in energy-efficient, biologically inspired computing.
Forward citations
Cited by 3 Pith papers
-
AIGOR: A Modular, Event-Driven Neuromorphic Architecture for Configurable SNN Inference
AIGOR generates modular, timestep-synchronized FPGA SNN cores from a declarative spec and matches snnTorch accuracy and NEST spike patterns on the same Versal cores across two FPGAs.
-
An Open-Source LFSR-Based Stochastic Leaky Integrate-and-Fire Neuron in SkyWater 130 nm: Design, Stochastic Characterisation, and Rate Coding
Open-source configurable LFSR-based stochastic LIF neuron in 130 nm CMOS with bit-exact model, stochastic characterization, and rate-coding sweeps.
-
Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
Presents four compatible standard-cell IP blocks for PVT sensing, stochastic LIF inference, on-chip STDP, and crossbar control in SkyWater 130 nm, verified in simulation with no silicon results reported.
discussion (0)
Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.