DEFT: Differentiable Automatic Test Pattern Generation

Jos\'e Moura; Shawn Blanton; Wei Li; Yang Zou; Yixin Liang

arxiv: 2512.23746 · v3 · pith:ZVCEKRSVnew · submitted 2025-12-26 · 💻 cs.SE

DEFT: Differentiable Automatic Test Pattern Generation

Wei Li , Yang Zou , Yixin Liang , Jos\'e Moura , Shawn Blanton This is my paper

Pith reviewed 2026-05-21 16:24 UTC · model grok-4.3

classification 💻 cs.SE

keywords differentiable ATPGtest pattern generationhard-to-detect faultscontinuous optimizationgradient-based methodscircuit testing

0 comments

The pith

DEFT reformulates automatic test pattern generation as continuous optimization to cut test pattern counts for hard-to-detect faults.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper shows how to recast the discrete problem of generating test patterns for integrated circuits as a continuous optimization task. The key step is a reparameterization that makes the continuous objective match the actual requirements for detecting faults in the circuit. With added techniques for efficient computation and stable gradients on complex circuits, DEFT produces significantly fewer patterns than commercial tools while still covering the necessary faults. A sympathetic reader would care because fewer test patterns mean shorter testing times and lower costs for manufacturing complex chips.

Core claim

DEFT reformulates the discrete ATPG problem as a continuous optimization task. It introduces a mathematically grounded reparameterization that aligns the expected continuous objective with discrete fault-detection semantics, enabling reliable gradient-based pattern generation. To ensure scalability and stability on deep circuit graphs, DEFT integrates a custom CUDA kernel for efficient forward-backward propagation and applies gradient normalization to mitigate vanishing gradients. On benchmarks it reduces pattern count by 27.3% on average and up to 75.9%.

What carries the argument

The reparameterization that aligns the continuous objective with discrete fault-detection semantics for gradient-based optimization on circuit graphs.

If this is right

DEFT reduces the number of test patterns by 27.3 percent on average compared to leading commercial tools.
It can produce partial assignment patterns with 19.3 percent fewer specified bits while detecting 35 percent more faults.
The method serves as a valuable complement to existing heuristic-based ATPG approaches.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

This differentiable formulation could be adapted to optimize other aspects of circuit design that currently rely on discrete searches.
Future work might combine DEFT with learning-based models to predict hard-to-detect faults more accurately before optimization.
The approach may scale to even larger circuits if the custom kernel is further optimized for modern hardware.

Load-bearing premise

The reparameterization makes the continuous loss function correspond accurately to the discrete outcome of whether a pattern detects a given fault.

What would settle it

A direct comparison on a new suite of large industrial circuits where DEFT fails to produce fewer patterns than the commercial tool while maintaining fault coverage would disprove the practical advantage.

Figures

Figures reproduced from arXiv: 2512.23746 by Jos\'e Moura, Shawn Blanton, Wei Li, Yang Zou, Yixin Liang.

**Figure 3.** Figure 3: Analogy Between Neural Network Training and [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗

**Figure 2.** Figure 2: illustrates the workflow of DEFT. Given a circuit netlist and a target fault list F, we first transform the circuit into a differentiable computation graph. We follow the well-established approach [14, 17] by modeling the circuit as a directed acyclic graph (DAG) whose nodes are logic gates and edges are wires. For nets with fan-out, we introduce a virtual node to explicitly represent each branch. The Boo… view at source ↗

**Figure 5.** Figure 5: Illustration of continuous value propagation using [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗

**Figure 6.** Figure 6: ATPG results of DEFT and commercial tool. y-axis is the number of detected faults. [PITH_FULL_IMAGE:figures/full_fig_p006_6.png] view at source ↗

**Figure 7.** Figure 7: Performance comparison of CUDA and PyTorch [PITH_FULL_IMAGE:figures/full_fig_p006_7.png] view at source ↗

read the original abstract

Modern IC complexity drives test pattern growth, with the majority of patterns targeting a small set of hard-to-detect (HTD) faults. This motivates new ATPG algorithms to improve test effectiveness specifically for HTD faults. This paper presents DEFT (Differentiable Automatic Test Pattern Generation), a new ATPG approach that reformulates the discrete ATPG problem as a continuous optimization task. DEFT introduces a mathematically grounded reparameterization that aligns the expected continuous objective with discrete fault-detection semantics, enabling reliable gradient-based pattern generation. To ensure scalability and stability on deep circuit graphs, DEFT integrates a custom CUDA kernel for efficient forward-backward propagation and applies gradient normalization to mitigate vanishing gradients. Compared to a leading commercial tool on a wide range of benchmarks, DEFT reduced the pattern count by 27.3% on average and by up to 75.9%. DEFT also supports practical ATPG settings such as partial assignment pattern generation, producing patterns with 19.3% fewer 0/1 bits while still detecting 35% more faults. These results indicate DEFT is a promising and effective ATPG engine, offering a valuable complement to existing heuristics.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

DEFT reformulates ATPG as differentiable optimization with a custom kernel and claims solid pattern-count wins, but the reparameterization's fidelity to discrete fault semantics on deep circuits still needs checking.

read the letter

The main thing here is that the authors recast test pattern generation as a continuous optimization problem instead of the usual discrete search. They add a reparameterization step meant to keep the gradients aligned with actual fault detection, plus a CUDA kernel and gradient normalization to handle large circuits without vanishing signals. On the benchmarks they ran, this cut pattern counts by about 27% on average versus a commercial tool, with bigger gains on some cases, and it also produced sparser partial-assignment patterns that still caught more faults. That is concrete progress for the hard-to-detect fault problem in EDA. The work is new in applying differentiable programming this way to ATPG rather than just tweaking existing heuristics. The empirical numbers are the strongest part; they show the method scales to real benchmarks and supports practical settings like partial assignments. The soft spot is the reparameterization itself. The abstract says it aligns the continuous objective with discrete semantics, but without the derivation or checks on reconvergent fanouts and sequential depth, it is not obvious that gradient steps on the surrogate actually improve true coverage rather than just the relaxed loss. If the relaxation introduces bias, the reported gains could shrink or disappear on harder industrial designs. No error bars or ablations are mentioned in what I have seen, which makes the claims harder to assess. This paper is for researchers and engineers working on ATPG and test compression in semiconductor design. A reader who cares about new algorithmic approaches to fault coverage will get value from the formulation and the reported speedups. It is coherent enough and grounded in a real problem to deserve serious referee time, even if the central alignment claim needs more evidence in revision.

Referee Report

2 major / 2 minor

Summary. The paper introduces DEFT, a differentiable automatic test pattern generation (ATPG) method that reformulates the discrete ATPG problem as a continuous optimization task. It proposes a mathematically grounded reparameterization to align the continuous objective with discrete fault-detection semantics, augmented by a custom CUDA kernel for forward-backward propagation on deep circuits and gradient normalization to mitigate vanishing gradients. On a range of benchmarks, DEFT is reported to reduce pattern counts by 27.3% on average (up to 75.9%) versus a leading commercial tool while also supporting partial-assignment generation with 19.3% fewer assigned bits and 35% more detected faults.

Significance. If the reparameterization reliably preserves discrete fault-detection semantics under gradient flow, the work would offer a meaningful complement to heuristic ATPG by enabling gradient-based search specifically for hard-to-detect faults. The reported pattern-count reductions would be practically relevant for test-cost reduction in IC manufacturing, and the custom CUDA kernel plus normalization demonstrate engineering attention to scalability on realistic circuit depths.

major comments (2)

[§3] §3 (reparameterization): the manuscript asserts that the continuous relaxation 'aligns the expected continuous objective with discrete fault-detection semantics' yet provides neither a derivation showing preservation of monotonicity/ranking after reconvergence and fanout nor an empirical check (e.g., correlation between surrogate loss decrease and true fault-coverage increase) on circuits containing reconvergent paths. This alignment is load-bearing for the claim that gradient descent produces patterns that actually improve discrete detection.
[§5] §5 (experimental results): the central performance figures (27.3% average, 75.9% max reduction) are presented without error bars, standard deviations across runs, or statistical significance tests, and without ablation isolating the reparameterization from the CUDA kernel and normalization; this weakens attribution of the gains to the core technical contribution.

minor comments (2)

[§4] The description of the custom CUDA kernel would benefit from a short pseudocode listing or explicit reference to the forward and backward passes to aid reproducibility.
Benchmark selection criteria and circuit characteristics (depth, reconvergence density) are not summarized in a table; adding such a table would help readers assess the scope of the claimed improvements.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the thoughtful and constructive comments on our manuscript. We address each of the major comments below and are prepared to revise the paper accordingly to strengthen the presentation and validation of our claims.

read point-by-point responses

Referee: [§3] §3 (reparameterization): the manuscript asserts that the continuous relaxation 'aligns the expected continuous objective with discrete fault-detection semantics' yet provides neither a derivation showing preservation of monotonicity/ranking after reconvergence and fanout nor an empirical check (e.g., correlation between surrogate loss decrease and true fault-coverage increase) on circuits containing reconvergent paths. This alignment is load-bearing for the claim that gradient descent produces patterns that actually improve discrete detection.

Authors: We appreciate this observation. The reparameterization in Section 3 is derived to ensure that the continuous objective is a faithful relaxation of the discrete fault detection, with the expectation that gradient steps correspond to improvements in detection probability. However, to more rigorously address potential issues with reconvergent paths, we will add a formal proof sketch demonstrating preservation of monotonicity under fanout and reconvergence in the revised manuscript. Additionally, we will include an empirical study correlating the decrease in the surrogate loss with increases in actual fault coverage on benchmark circuits known to have reconvergent paths. revision: yes
Referee: [§5] §5 (experimental results): the central performance figures (27.3% average, 75.9% max reduction) are presented without error bars, standard deviations across runs, or statistical significance tests, and without ablation isolating the reparameterization from the CUDA kernel and normalization; this weakens attribution of the gains to the core technical contribution.

Authors: We agree that including variability measures and ablations would improve the robustness of the experimental claims. In the revised version, we will report standard deviations over multiple independent runs with different random seeds and include p-values from statistical tests comparing DEFT to the commercial tool. Furthermore, we will add an ablation study that isolates the effect of the reparameterization by comparing the full DEFT against a variant that uses a simpler continuous relaxation while retaining the CUDA kernel and gradient normalization. This will help attribute the performance gains more clearly to the proposed reparameterization. revision: yes

Circularity Check

0 steps flagged

No circularity: reparameterization is presented as novel ansatz without reduction to inputs

full rationale

The provided abstract and context introduce DEFT as a reformulation of discrete ATPG into continuous optimization via a 'mathematically grounded reparameterization' that aligns objectives with fault-detection semantics, followed by custom CUDA kernels and gradient normalization for scalability. No equations, fitted parameters, or self-citations are quoted that would make any prediction or result equivalent to its inputs by construction. The performance claims rest on empirical comparison to a commercial tool rather than on quantities defined in terms of the method's own outputs. This is a standard application of differentiable programming to a new domain, with the derivation chain self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 1 invented entities

The central claim rests on the effectiveness of the reparameterization for aligning continuous and discrete objectives and on the assumption that gradient normalization suffices for stability on deep circuit graphs; no free parameters or new physical entities are mentioned.

axioms (1)

domain assumption Gradient-based methods can be made to respect the discrete 0/1 semantics of circuit fault detection through reparameterization
Invoked to justify turning the discrete ATPG problem into a continuous optimization task.

invented entities (1)

Differentiable reparameterization for ATPG no independent evidence
purpose: Align continuous objective with discrete fault-detection semantics
Introduced to enable reliable gradient-based pattern generation

pith-pipeline@v0.9.0 · 5738 in / 1399 out tokens · 56343 ms · 2026-05-21T16:24:15.462794+00:00 · methodology

discussion (0)

Lean theorems connected to this paper

Citations machine-checked in the Pith Canon. Every link opens the source theorem in the public Lean library.

IndisputableMonolith/Cost/FunctionalEquation.lean washburn_uniqueness_aczel unclear

?

unclear
Relation between the paper passage and the cited Recognition theorem.

DEFT introduces a mathematically grounded reparameterization that aligns the expected continuous objective with discrete fault-detection semantics... hybrid surrogate... L_exploit = E[ S_f(˜x_soft) · I_f(˜x_hard) ]
IndisputableMonolith/Foundation/RealityFromDistinction.lean reality_from_one_distinction unclear

?

unclear
Relation between the paper passage and the cited Recognition theorem.

custom CUDA kernel... gradient normalization... probabilistic logic relaxations

What do these tags mean?

matches: The paper's claim is directly supported by a theorem in the formal canon.
supports: The theorem supports part of the paper's argument, but the paper may add assumptions or extra steps.
extends: The paper goes beyond the formal theorem; the theorem is a base layer rather than the whole result.
uses: The paper appears to rely on the theorem as machinery.
contradicts: The paper's claim conflicts with a theorem or certificate in the canon.
unclear: Pith found a possible connection, but the passage is too broad, indirect, or ambiguous to say the theorem truly supports the claim.

Reference graph

Works this paper leans on

20 extracted references · 20 canonical work pages · 1 internal anchor

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Cell-aware test,

F. Hapke, W. Redemund, A. Glowatz, J. Rajski, M. Reese, M. Hustava, M. Keim, J. Schloeffel, and A. Fast, “Cell-aware test, ”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 9, pp. 1396–1409, 2014

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W. Li, C. Nigh, D. Duvalsaint, and S. Mitra, “Pepr: Pseudo-exhaustive physically- aware region testing, ” in2022 IEEE International Test Conference (ITC). IEEE, 2022, pp. 314–323

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W. Li, H. Lyu, S. Liang, T. Wang, and H. Li, “Smartatpg: Learning-based automatic test pattern generation with graph convolutional network and reinforcement learning, ” inProceedings of the 61st ACM/IEEE Design Automation Conference, 2024, pp. 1–6

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Z. Chao, X. Zhang, X. Zhang, J. Mu, Z. Liu, S. Liang, S. Cai, J. Ye, X. Li, and H. Li, “Pastatpg: A hybrid atpg framework for better test compaction with partial assignment sat, ” in2025 62nd ACM/IEEE Design Automation Conference (DAC). IEEE, 2025, pp. 1–7

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Goel, “An implicit enumeration algorithm to generate tests for combinational logic circuits, ”IEEE transactions on Computers, vol. 100, no. 3, pp. 215–222, 1981

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Y. Lin, S. Dhar, W. Li, H. Ren, B. Khailany, and D. Z. Pan, “Dreamplace: Deep learn- ing toolkit-enabled gpu acceleration for modern vlsi placement, ” inProceedings of the 56th Annual Design Automation Conference 2019, 2019, pp. 1–6

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Dgr: Dif- ferentiable global router,

W. Li, R. Liang, A. Agnesina, H. Yang, C.-T. Ho, A. Rajaram, and H. Ren, “Dgr: Dif- ferentiable global router, ” inProceedings of the 61st ACM/IEEE Design Automation Conference, 2024, pp. 1–6

work page 2024

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Y.-C. Lu, Z. Guo, K. Kunal, R. Liang, and H. Ren, “Insta: An ultra-fast, differ- entiable, statistical static timing analysis engine for industrial physical design applications, ” in2025 62nd ACM/IEEE Design Automation Conference (DAC). IEEE, 2025, pp. 1–7

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Z. Wang, J. Wang, Q. Yang, Y. Bai, X. Li, L. Chen, J. Hao, M. Yuan, B. Li, Y. Zhang et al., “Towards next-generation logic synthesis: A scalable neural circuit genera- tion framework, ”Advances in Neural Information Processing Systems, vol. 37, pp. 99 202–99 231, 2024

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F. Petersen, C. Borgelt, H. Kuehne, and O. Deussen, “Deep differentiable logic gate networks, ”Advances in Neural Information Processing Systems, vol. 35, pp. 2006–2018, 2022

work page 2006

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Safety-guided test generation for structural faults,

X. Tan, D. Thapar, D. Sahoo, A. Chaudhuri, S. Banerjee, K. Chakrabarty, and R. Parekhji, “Safety-guided test generation for structural faults, ” in2024 IEEE International Test Conference (ITC). IEEE, 2024, pp. 233–242

work page 2024

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Categorical Reparameterization with Gumbel-Softmax

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work page internal anchor Pith review Pith/arXiv arXiv 2016

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Differentiable integer linear programming,

Z. Geng, J. Wang, X. Li, F. Zhu, J. Hao, B. Li, and F. Wu, “Differentiable integer linear programming, ” inThe Thirteenth International Conference on Learning Representations, 2025

work page 2025

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Defect modeling using fault tuples,

R. D. Blanton, K. N. Dwarakanath, and R. Desineni, “Defect modeling using fault tuples, ”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 11, pp. 2450–2464, 2006

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Sun Microsystems, Inc., “Opensparc t2 system-on-chip (soc) design, ” https:// www.oracle.com/servers/technologies/opensparc-t2-page.html, 2008

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