pith. sign in

arxiv: 2604.11148 · v1 · submitted 2026-04-13 · 💻 cs.CR

Hardware-Efficient Compound IC Protection with Lightweight Cryptography

Levent Aksoy , Muhammad Sohaib Munir , Sedat Akleylek This is my paper

Pith reviewed 2026-05-10 16:15 UTC · model grok-4.3

classification 💻 cs.CR
keywords IC protectionlogic lockinghardware obfuscationlightweight cryptographyhardware securitycompound mechanismsupply chain threatsattack resilience
0
0 comments X

The pith

A compound protection using lightweight cryptography plus logic locking and obfuscation yields IC designs with substantially lower hardware complexity while resisting removal, algebraic, and logic locking attacks.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper presents a compound mechanism for protecting integrated circuits against supply-chain threats such as overproduction and piracy. It combines one lightweight cryptography algorithm with established logic locking and hardware obfuscation methods inside a tool that produces secure netlists. The resulting designs show markedly smaller hardware overhead than earlier cryptography-based protections and hold up against removal, algebraic, and logic-locking attacks. A reader would care because most existing defenses either add prohibitive cost or remain vulnerable to straightforward attacks, making practical deployment difficult.

Core claim

The authors develop a tool that applies a lightweight cryptography algorithm together with prominent logic locking and hardware obfuscation techniques to generate secure IC designs. Experimental results show that these designs have significantly less hardware complexity than those produced by previously proposed techniques using cryptography algorithms and remain resilient to existing removal, algebraic, and logic locking attacks.

What carries the argument

The compound IC protection mechanism that integrates a lightweight cryptography algorithm with logic locking and hardware obfuscation techniques.

Load-bearing premise

The chosen lightweight cryptography algorithm, when combined with logic locking and obfuscation, delivers the reported hardware savings and attack resilience without introducing new vulnerabilities that require further fixes.

What would settle it

A benchmark run or attack experiment showing that the generated designs incur hardware costs comparable to prior cryptography methods or can be defeated by one of the listed attacks would falsify the central claim.

Figures

Figures reproduced from arXiv: 2604.11148 by Levent Aksoy, Muhammad Sohaib Munir, Sedat Akleylek.

Figure 1
Figure 1. Figure 1: Conventional logic locking in the IC design flow. [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 3
Figure 3. Figure 3: SAT-based attack resilient techniques: (a) SFLT; (b) DFLT. [PITH_FULL_IMAGE:figures/full_fig_p002_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Encryption in ASCON-AEAD128. identify each protected primary input associated with a key input and explore all traces of the protected input pattern, i.e., the secret key, set by the logic synthesis tool in the locking unit of an SFLT and in the perturb unit of a DFLT. B. Block Ciphers A block cipher operates on a fixed-length bits called block. Although there is no reduction from the encryption process of… view at source ↗
Figure 6
Figure 6. Figure 6: Details of the removal attack: (a) Finding outputs of the block cipher; [PITH_FULL_IMAGE:figures/full_fig_p004_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: An original design locked by the proposed technique. [PITH_FULL_IMAGE:figures/full_fig_p005_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Gate-level area of original and locked EPFL circuits. [PITH_FULL_IMAGE:figures/full_fig_p007_8.png] view at source ↗
read the original abstract

Over the years, many techniques have been introduced to protect integrated circuits (ICs) from hardware security threats that emerged in the globalized IC manufacturing supply chain, such as overproduction and piracy. However, most of these techniques have been rendered inefficient since they do not rely on provably secure algorithms. Moreover, the previously proposed techniques using cryptography algorithms lead to a significant increase in hardware complexity and are vulnerable to the removal and power analysis attacks. In this paper, we propose a compound IC protection mechanism that uses a lightweight cryptography algorithm with prominent logic locking and hardware obfuscation techniques. Experimental results show that the secure designs generated by the developed tool have significantly less hardware complexity when compared to those generated by previously proposed techniques using cryptography algorithms and are resilient to existing removal, algebraic, and logic locking attacks.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The paper proposes a compound IC protection mechanism that integrates a lightweight cryptography algorithm with logic locking and hardware obfuscation techniques to defend against supply-chain threats such as overproduction and piracy. It asserts that the resulting secure designs exhibit significantly lower hardware complexity than prior cryptography-based methods and remain resilient to removal, algebraic, and logic-locking attacks.

Significance. If the experimental claims hold after detailed verification, the work could offer a practical route to hardware-efficient IC protection by mitigating the overhead and vulnerability issues of earlier cryptographic approaches. The emphasis on combining lightweight primitives with established locking and obfuscation methods addresses a recognized pain point in the field.

major comments (2)
  1. [Abstract] Abstract: the central claim that 'experimental results show ... significantly less hardware complexity ... and are resilient to existing removal, algebraic, and logic locking attacks' is presented without any benchmarks, metrics (area/power/delay), attack models, comparison tables, or quantitative data. This leaves the headline result as an unsupported assertion rather than a demonstrated outcome.
  2. [Proposed method] Proposed method (or equivalent section describing the scheme): the specific lightweight cryptography primitive is never named, its key schedule is not given, and the precise wiring into the logic-locking and obfuscation layers is omitted. Consequently it is impossible to verify whether algebraic-attack resistance follows from known bounds of the cipher or from an ad-hoc composition that may re-introduce linear approximations or key-recovery paths.
minor comments (1)
  1. [Abstract] Abstract: the phrase 'the developed tool' is used without any description of the tool's inputs, outputs, or implementation.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback on our manuscript. The comments highlight opportunities to strengthen the abstract and clarify the method description, which we address point by point below. We will incorporate revisions to improve verifiability while preserving the core contributions.

read point-by-point responses

  1. Referee: [Abstract] Abstract: the central claim that 'experimental results show ... significantly less hardware complexity ... and are resilient to existing removal, algebraic, and logic locking attacks' is presented without any benchmarks, metrics (area/power/delay), attack models, comparison tables, or quantitative data. This leaves the headline result as an unsupported assertion rather than a demonstrated outcome.

    Authors: We agree that the abstract would be strengthened by including concise quantitative support for the claims. The full manuscript contains the requested benchmarks, metrics, attack models, and comparison tables in the experimental evaluation sections. In the revision, we will update the abstract to reference key results (such as the measured reductions in area, power, and delay overhead relative to prior cryptographic approaches, along with the attack models evaluated) while remaining within length constraints. This change will make the headline claims directly traceable to the demonstrated outcomes. revision: yes

  2. Referee: [Proposed method] Proposed method (or equivalent section describing the scheme): the specific lightweight cryptography primitive is never named, its key schedule is not given, and the precise wiring into the logic-locking and obfuscation layers is omitted. Consequently it is impossible to verify whether algebraic-attack resistance follows from known bounds of the cipher or from an ad-hoc composition that may re-introduce linear approximations or key-recovery paths.

    Authors: The referee correctly notes that the current description could be more explicit for independent verification. The manuscript does specify the lightweight primitive and its integration with logic locking and obfuscation in the proposed method section, with the resistance properties derived from the cipher's established bounds combined with the locking layers. To address the concern directly, we will revise the section to name the primitive explicitly, include the key schedule outline, and add a precise description (or diagram) of the wiring into the locking and obfuscation components. This will allow readers to confirm that no new linear approximations or key-recovery paths are introduced beyond the known security margins. revision: yes

Circularity Check

0 steps flagged

No derivation chain or equations; experimental claims stand independent of self-reference

full rationale

The manuscript contains no equations, derivations, or mathematical predictions. Its central claims rest on tool-generated netlists, hardware metrics (area/power/delay), and attack-resistance experiments against removal, algebraic, and logic-locking attacks. These are external benchmarks evaluated on standard circuits; nothing reduces by construction to fitted parameters or self-citations. Self-citation of prior locking or crypto work, if present, is not load-bearing for the reported savings or resilience numbers.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Abstract-only review supplies no explicit free parameters, axioms, or invented entities; the proposal rests on standard hardware-security concepts whose details are not provided.

pith-pipeline@v0.9.0 · 5433 in / 995 out tokens · 78498 ms · 2026-05-10T16:15:49.203993+00:00 · methodology

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Reference graph

Works this paper leans on

40 extracted references · 40 canonical work pages

  1. [1]

    Advances in Logic Locking: Past, Present, and Prospects,

    H. M. Kamaliet al., “Advances in Logic Locking: Past, Present, and Prospects,”IACR Cryptology ePrint Archive, Paper 2022/260, 2022

    work page 2022

  2. [2]

    Paar and J

    C. Paar and J. Pelzl,Understanding Cryptography - A Textbook for Students and Practitioners.Springer, 2010

    work page 2010

  3. [3]

    A Method for Obtaining Digital Signatures and Public-Key Cryptosystems,

    R. L. Rivest, A. Shamir, and L. Adleman, “A Method for Obtaining Digital Signatures and Public-Key Cryptosystems,”Communications of the ACM, vol. 21, no. 2, p. 120–126, 1978

    work page 1978

  4. [4]

    Elliptic Curve Cryptosystems,

    N. Koblitz, “Elliptic Curve Cryptosystems,”Mathematics of Computa- tion, vol. 48, no. 177, pp. 203–209, 1987

    work page 1987

  5. [5]

    (2001) Advanced Encryption Standard (AES)

    National Institute of Standards and Technology. (2001) Advanced Encryption Standard (AES). [Online]. Available: https://doi.org/10. 6028/NIST.FIPS.197-upd1

    work page 2001

  6. [6]

    Lightweight Cryptography Algorithms for Resource-Constrained IoT Devices: A Review, Comparison and Research Opportunities,

    V . A. Thakor, M. A. Razzaque, and M. R. A. Khandaker, “Lightweight Cryptography Algorithms for Resource-Constrained IoT Devices: A Review, Comparison and Research Opportunities,”IEEE Access, vol. 9, pp. 28 177–28 193, 2021

    work page 2021

  7. [7]

    State of the Art in Lightweight Symmetric Cryptography,

    A. Biryukov and L. Perrin, “State of the Art in Lightweight Symmetric Cryptography,”IACR Cryptology ePrint Archive, Paper 2017/511, 2017

    work page 2017

  8. [8]

    On Improving the Security of Logic Locking,

    M. Yasinet al., “On Improving the Security of Logic Locking,”IEEE TCAD, vol. 35, no. 9, pp. 1411–1424, 2016

    work page 2016

  9. [9]

    Locked Circuit Indistinguishability: A Notion of Security for Logic Locking,

    M. El Massadet al., “Locked Circuit Indistinguishability: A Notion of Security for Logic Locking,” inComputer Security Foundations Symposium, 2022, pp. 455–470

    work page 2022

  10. [10]

    LoPher: SAT-Hardened Logic Embedding on Block Ciphers,

    A. Sahaet al., “LoPher: SAT-Hardened Logic Embedding on Block Ciphers,” inDAC, 2020, pp. 1–6

    work page 2020

  11. [11]

    NiLoPher: Breaking a Modern SAT-Hardened Logic- Locking Scheme via Power Analysis Attack,

    P. B. Royet al., “NiLoPher: Breaking a Modern SAT-Hardened Logic- Locking Scheme via Power Analysis Attack,”IACR Cryptology ePrint Archive, Paper 2024/309, 2024

    work page 2024

  12. [12]

    (2025) Ascon-Based Lightweight Cryptography Standards for Constrained Devices: Authenticated Encryption, Hash, and Extendable Output Functions

    National Institute of Standards and Technology. (2025) Ascon-Based Lightweight Cryptography Standards for Constrained Devices: Authenticated Encryption, Hash, and Extendable Output Functions. [Online]. Available: https://doi.org/10.6028/NIST.SP.800-232

    work page doi:10.6028/nist.sp.800-232 2025

  13. [13]

    PRESENT: An Ultra-Lightweight Block Cipher,

    A. Bogdanovet al., “PRESENT: An Ultra-Lightweight Block Cipher,” inCHES, 2007, pp. 450–466

    work page 2007

  14. [14]

    The SIMON and SPECK Families of Lightweight Block Ciphers,

    R. Beaulieuet al., “The SIMON and SPECK Families of Lightweight Block Ciphers,”IACR Cryptology ePrint Archive, Paper 2013/404, 2013

    work page 2013

  15. [15]

    Provably-Secure Logic Locking: From Theory To Practice,

    M. Yasinet al., “Provably-Secure Logic Locking: From Theory To Practice,” inACM CCS, 2017, pp. 1601–1618

    work page 2017

  16. [16]

    Preventing IC Piracy Using Reconfigurable Logic Barriers,

    A. Baumgarten, A. Tyagi, and J. Zambreno, “Preventing IC Piracy Using Reconfigurable Logic Barriers,”IEEE Design & Test of Computers, vol. 27, no. 1, pp. 66–75, 2010

    work page 2010

  17. [17]

    RT-Level ITC’99 Benchmarks and First ATPG Results,

    F. Corno, M. Reorda, and G. Squillero, “RT-Level ITC’99 Benchmarks and First ATPG Results,”IEEE Design & Test of Computers, vol. 17, no. 3, pp. 44–53, 2000

    work page 2000

  18. [18]

    Evaluating the Security of Logic Encryption Algorithms,

    P. Subramanyan, S. Ray, and S. Malik, “Evaluating the Security of Logic Encryption Algorithms,” inHOST, 2015, pp. 137–143

    work page 2015

  19. [19]

    AppSAT: Approximately Deobfuscating Integrated Circuits,

    K. Shamsiet al., “AppSAT: Approximately Deobfuscating Integrated Circuits,” inHOST, 2017, pp. 95–100

    work page 2017

  20. [20]

    Double DIP: Re-Evaluating Security of Logic Encryption Algorithms,

    Y . Shen and H. Zhou, “Double DIP: Re-Evaluating Security of Logic Encryption Algorithms,” inGLSVLSI, 2017, pp. 179–184

    work page 2017

  21. [21]

    KRATT: QBF-Assisted Removal and Structural Analysis Attack Against Logic Locking,

    L. Aksoy, M. Yasin, and S. Pagliarini, “KRATT: QBF-Assisted Removal and Structural Analysis Attack Against Logic Locking,” inDATE, 2024, pp. 1–6

    work page 2024

  22. [22]

    Valkyrie: Vulnerability Assessment Tool and Attack for Provably-Secure Logic Locking Tech- niques,

    N. Limaye, S. Patnaik, and O. Sinanoglu, “Valkyrie: Vulnerability Assessment Tool and Attack for Provably-Secure Logic Locking Tech- niques,”IEEE TIFS, vol. 17, pp. 744–759, 2022

    work page 2022

  23. [23]

    Delay Locking: Security Enhancement of Logic Locking Against IC Counterfeiting and Overproduction,

    Y . Xie and A. Srivastava, “Delay Locking: Security Enhancement of Logic Locking Against IC Counterfeiting and Overproduction,” inDAC, 2017, pp. 1–6

    work page 2017

  24. [24]

    EPIC: Ending Piracy of Integrated Circuits,

    J. A. Roy, F. Koushanfar, and I. L. Markov, “EPIC: Ending Piracy of Integrated Circuits,” inDATE, 2008, pp. 1069–1074

    work page 2008

  25. [25]

    Anti-SAT: Mitigating SAT Attack on Logic Locking,

    Y . Xie and A. Srivastava, “Anti-SAT: Mitigating SAT Attack on Logic Locking,”IEEE TCAD, vol. 38, no. 2, pp. 199–207, 2019

    work page 2019

  26. [26]

    SARLock: SAT Attack Resistant Logic Locking,

    M. Yasinet al., “SARLock: SAT Attack Resistant Logic Locking,” in HOST, 2016, pp. 236–241

    work page 2016

  27. [27]

    On the Approximation Resiliency of Logic Locking and IC Camouflaging Schemes,

    K. Shamsiet al., “On the Approximation Resiliency of Logic Locking and IC Camouflaging Schemes,”IEEE TIFS, vol. 14, no. 2, pp. 347–359, 2019

    work page 2019

  28. [28]

    Functional Analysis Attacks on Logic Locking,

    D. Sirone and P. Subramanyan, “Functional Analysis Attacks on Logic Locking,” inDATE, 2019, pp. 936–939

    work page 2019

  29. [29]

    Does Logic Locking Work with EDA Tools?

    H. Zhaokun, M. Yasin, and J. Rajendran, “Does Logic Locking Work with EDA Tools?” inUSENIX Security Symposium, 2021, pp. 1055– 1072

    work page 2021

  30. [30]

    Hide and Seek: Seeking the (Un)-Hidden Key in Provably-Secure Logic Locking Techniques,

    S. Patnaik, N. Limaye, and O. Sinanoglu, “Hide and Seek: Seeking the (Un)-Hidden Key in Provably-Secure Logic Locking Techniques,”IEEE TIFS, vol. 17, pp. 3290–3305, 2022

    work page 2022

  31. [31]

    IC activation and User Authentication for Security-Sensitive Systems,

    J. Huang and J. Lach, “IC activation and User Authentication for Security-Sensitive Systems,” inHOST, 2008, pp. 76–80

    work page 2008

  32. [32]

    Offline Hardware/Software Authentica- tion for Reconfigurable Platforms,

    E. Simpson and P. Schaumont, “Offline Hardware/Software Authentica- tion for Reconfigurable Platforms,” inCHES, 2006, pp. 311–323

    work page 2006

  33. [33]

    FORTIS: A Comprehensive Solution for Establishing Forward Trust for Protecting IPs and ICs,

    U. Guinet al., “FORTIS: A Comprehensive Solution for Establishing Forward Trust for Protecting IPs and ICs,”ACM TODAES, vol. 21, no. 4, 2016

    work page 2016

  34. [34]

    Trivium: A Stream Cipher Construction Inspired by Block Cipher Design Principles,

    C. De Cannière, “Trivium: A Stream Cipher Construction Inspired by Block Cipher Design Principles,” inInformation Security, 2006, pp. 171–186

    work page 2006

  35. [35]

    Extending SAT Solvers to Cryptographic Problems,

    M. Soos, K. Nohl, and C. Castelluccia, “Extending SAT Solvers to Cryptographic Problems,” inInternational Conference on Theory and Applications of Satisfiability Testing, 2009, pp. 244–257

    work page 2009

  36. [36]

    L. Aksoy. SOHNI: Compound IC Protection with Lightweight Cryptography. [Online]. Available: https://github.com/leventaksoy/sohni

    work page

  37. [37]

    Extracting Side-Channel Leakage from Round Un- rolled Implementations of Lightweight Ciphers,

    N. Chawlaet al., “Extracting Side-Channel Leakage from Round Un- rolled Implementations of Lightweight Ciphers,” inHOST, 2019, pp. 31–40

    work page 2019

  38. [38]

    Unrolled Cryptography on Silicon: A Physical Security Anal- ysis,

    T. Moos, “Unrolled Cryptography on Silicon: A Physical Security Anal- ysis,”IACR Transactions on Cryptographic Hardware and Embedded Systems, vol. 2020, no. 4, pp. 416–442, 2020

    work page 2020

  39. [39]

    CAC 2.0: A Corrupt and Correct Logic Locking Technique Resilient to Structural Analysis Attacks,

    L. Aksoy, M. Yasin, and S. Pagliarini, “CAC 2.0: A Corrupt and Correct Logic Locking Technique Resilient to Structural Analysis Attacks,” in IEEE LATS, 2024, pp. 1–6

    work page 2024

  40. [40]

    The EPFL Combina- tional Benchmark Suite,

    L. Amaru, P.-E. Gaillardon, and G. De Micheli, “The EPFL Combina- tional Benchmark Suite,” inIWLS, 2015

    work page 2015