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arxiv: 2605.30814 · v1 · pith:RWYZAFLSnew · submitted 2026-05-29 · 💻 cs.AR

A Reconfigurable Computing In-Memory Macro with Charge-sharing-based Weighted Accumulator

Junyi Yang , Shuai Dong , Zhengnan Fu , Hongyang Shang , Arindam Basu This is my paper

Pith reviewed 2026-06-28 20:42 UTC · model grok-4.3

classification 💻 cs.AR
keywords in-memory computingSRAManalog computingreconfigurable arraycharge-sharing accumulatordual-8T bitcellADC overhead reductionneural network accelerator
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The pith

A reconfigurable 256x128 SRAM in-memory array integrates a low-overhead ADC, charge-sharing accumulator, and dual-8T bitcells to support 1-7 bit inputs and weights while addressing ADC area, latency, and voltage swing limits.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper sets out to build a multi-bit SRAM analog computing-in-memory macro that overcomes three barriers: large ADC area cost, slow handling of multi-bit inputs, and restricted read bitline voltage range. It does so with three specific additions inside a 256x128 array that can be configured for 1-7b inputs, 2-4b weights, and 1-7b outputs. An in-memory ADC is shown to take only 3 percent area while delivering a 9x area improvement over earlier versions. A charge-sharing weighted accumulator shortens the time needed for multi-bit accumulation. A dual-8T bitcell with decoupled read path and under-driven cascode read wordline raises current linearity and usable bitline voltage. If these elements work together, the macro offers a concrete route to more area-efficient and faster analog in-memory computation for variable-precision workloads.

Core claim

The proposed macro achieves its reconfigurability and performance through an IMADC that occupies only 3 percent area with a 9x improvement over prior IMADCs, a BSCHA that reduces latency by 1.9x relative to PWM and 6.6x relative to bit-slicing, and a dual-8T bitcell that stores ternary weights via a decoupled read path combined with read wordline under-driven cascode, delivering 7x better unit discharge current linearity and 3.5x greater usable read bitline voltage.

What carries the argument

The charge-sharing-based weighted accumulator (BSCHA) paired with the in-memory ADC (IMADC) and the dual-8T bitcell that uses a decoupled read path plus under-driven cascode read wordline to control discharge current.

If this is right

  • The array can be programmed for different input, weight, and output precisions without redesigning the core hardware.
  • Multi-bit input processing completes in less time than either PWM or bit-slicing approaches.
  • The small IMADC leaves most of the die area available for the memory array itself.
  • Ternary weights become practical inside a standard SRAM-style cell layout.
  • Higher usable read bitline voltage allows more reliable summation of discharge currents across the column.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The reconfigurability may reduce the need for separate accelerators tuned to each precision level in a single system.
  • The cascode read technique could be examined for compatibility with other bitcell topologies that also suffer from nonlinear discharge.
  • If the area and latency numbers scale with array size, larger macros might still keep the same relative overhead.
  • The design leaves open the question of how the same techniques perform when the array is embedded inside a larger digital SoC with shared power rails.

Load-bearing premise

The measured area, latency, linearity, and voltage gains remain valid when process variation, temperature, and supply noise are present and without large unstated penalties in power or yield.

What would settle it

Silicon measurements on a fabricated chip that show the IMADC area rising above 3 percent of the macro or the BSCHA latency reduction dropping below the stated 1.9x and 6.6x factors under standard operating conditions.

Figures

Figures reproduced from arXiv: 2605.30814 by Arindam Basu, Hongyang Shang, Junyi Yang, Shuai Dong, Zhengnan Fu.

Figure 1
Figure 1. Figure 1: System latency and ADC area overhead: (a) System latency (Our [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: (a) Hardware structure of the proposed dual 8T SRAM CIM and [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: (a) Detailed circuit and timing diagram of MAC columns and IMADC. (b) Internal signals of SA. (c) IMADC principle. [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: (a) Schematic of RWLUDC. (b) Voltage swings and current variations [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Self-biased voltage buffer (a) Circuit Diagram. (b) Monte Carlo [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Method for multi-bit weight with two cases (3-bit and 4-bit weights). [PITH_FULL_IMAGE:figures/full_fig_p007_6.png] view at source ↗
Figure 9
Figure 9. Figure 9: ADC error distribution (ADC error= (simulated ADC output [PITH_FULL_IMAGE:figures/full_fig_p008_9.png] view at source ↗
Figure 7
Figure 7. Figure 7: (a) Effective circuit model for generation of differential MAC voltage [PITH_FULL_IMAGE:figures/full_fig_p008_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: (a) Monte Carlo simulation for buffer noise. (b) Monte Carlo [PITH_FULL_IMAGE:figures/full_fig_p008_8.png] view at source ↗
Figure 10
Figure 10. Figure 10: (a) SA schematic. (b) Monte Carlo simulation for SA noise. (c) [PITH_FULL_IMAGE:figures/full_fig_p009_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Post layout simulation versus theoretical 4-bit IMADC output across temperature variations (0°C, 70°C, 27°C) and different process corners (TT, [PITH_FULL_IMAGE:figures/full_fig_p010_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: The inference accuracy results with hardware-simulated ADC noise [PITH_FULL_IMAGE:figures/full_fig_p010_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: Weight sparsity result across each layer for VGG-8 on CIFAR-10 [PITH_FULL_IMAGE:figures/full_fig_p011_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: Throughput under different input, output, and weight resolutions. [PITH_FULL_IMAGE:figures/full_fig_p011_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: The partial MACP/N distribution of (a) Proposed method and (b) PWM mode based on 3-bit input for MNIST. Their corresponding voltages on [PITH_FULL_IMAGE:figures/full_fig_p012_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: (a) Energy breakdown (4-bit input/output and 2-bit weight) based [PITH_FULL_IMAGE:figures/full_fig_p012_16.png] view at source ↗
Figure 18
Figure 18. Figure 18: System throughput and energy efficiency comparison with previous [PITH_FULL_IMAGE:figures/full_fig_p013_18.png] view at source ↗
read the original abstract

SRAM-based analog computing-in-memory demonstrates outstanding efficiency. However, it faces three critical challenges: significant ADC overhead, high latency for multi-bit inputs, and limited read bitline voltage. To address these issues, this work proposes a multi-bit highly reconfigurable 256x128 in-memory computing array supporting 1-7b input, 2-4b weight, and 1-7b output. Three key innovations are introduced: 1) The IMADC occupies only 3% area overhead, achieving a 9x improvement compared to previous IMADC; 2) The BSCHA reduces latency by 1.9x and 6.6x compared to traditional pulse-width modulation (PWM) and bit-slicing modes, respectively; 3) A dual-8T bitcell enabling ternary weight storage through a decoupled read path, integrated with a read wordline under-driven cascode technique, improves linearity of unit discharge current by 7x and increases the usable read bitline voltage by 3.5x.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

0 major / 1 minor

Summary. The manuscript presents a reconfigurable 256x128 SRAM-based analog computing-in-memory array supporting 1-7b inputs, 2-4b weights, and 1-7b outputs. It introduces three main contributions: an IMADC with 3% area overhead achieving 9x improvement over prior designs, a BSCHA reducing latency by 1.9x versus PWM and 6.6x versus bit-slicing modes, and a dual-8T bitcell with decoupled read path plus read-wordline under-driven cascode that improves unit discharge current linearity by 7x and usable RBL voltage range by 3.5x.

Significance. If the reported gains hold, the work meaningfully advances CiM hardware by directly tackling ADC area, multi-bit latency, and RBL voltage limitations through concrete circuit techniques. The explicit quantitative comparisons to established baselines (PWM, bit-slicing, prior IMADCs) and the parameter choices that produce the stated improvements provide clear, falsifiable benchmarks for the community.

minor comments (1)
  1. [Abstract] Abstract: the quantitative claims would be easier to assess if the abstract briefly indicated the simulation conditions or baseline references used for the 9x, 1.9x, 6.6x, 7x, and 3.5x figures.

Simulated Author's Rebuttal

0 responses · 0 unresolved

We thank the referee for the positive summary of our work on the reconfigurable 256x128 CIM array, the IMADC, BSCHA accumulator, and dual-8T bitcell, and for recommending minor revision. The referee's description accurately captures the claimed improvements in ADC area, latency, and RBL linearity/voltage range.

Circularity Check

0 steps flagged

No significant circularity; hardware claims rest on explicit design comparisons

full rationale

The manuscript describes a reconfigurable SRAM-based in-memory computing macro with three circuit-level innovations (IMADC, BSCHA, dual-8T bitcell with under-driven cascode). All quantitative claims (3% area, 9x improvement, 1.9x/6.6x latency reductions, 7x linearity, 3.5x voltage range) are presented as outcomes of concrete implementation choices and direct comparisons to prior PWM/bit-slicing baselines. No equations, fitted parameters, predictions, or first-principles derivations appear; the work contains no self-definitional loops, fitted-input-as-prediction steps, or load-bearing self-citations that reduce the central claims to their own inputs. The derivation chain is therefore self-contained against external benchmarks and receives the default non-circularity finding.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Hardware circuit design paper; the abstract contains no free parameters, mathematical axioms, or newly postulated physical entities.

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