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arxiv: 2606.04908 · v1 · pith:4TGJPEHZnew · submitted 2026-06-03 · 💻 cs.OS

GNStor: Design of GPU-Native High-Performance Remote All-Flash Array

Shushu Yi , Wenbo Wu , Guoci Chen , Junrong Zhu , Shengwen Liang , Mao Bo , Chenying Huan , Chen Tian
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Jie Zhang
This is my paper

Pith reviewed 2026-06-28 03:21 UTC · model grok-4.3

classification 💻 cs.OS
keywords GPU-native storageremote all-flash arrayNVMe over RDMACPU-bypass I/Odecentralized AFA enginehigh-performance storageGPU direct accessSSD firmware integration
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The pith

GNStor lets GPUs access remote all-flash arrays directly without CPU involvement to reach 3.2 times higher I/O throughput.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper seeks to establish that existing GPU-AFA setups incur heavy overhead because the CPU still handles all remote I/O orchestration and AFA functions. By redesigning the stack so the GPU itself starts and manages requests to remote SSDs, the system removes CPU-GPU handoffs and traffic amplification. A sympathetic reader would care because GPU applications increasingly rely on large shared remote storage, and any reduction in I/O friction directly speeds up those workloads. The design keeps required AFA features intact by moving them into the SSDs rather than leaving them on the CPU.

Core claim

GNStor is a GPU-native remote AFA system built around GNoR, a GPU-centric NVMe over RDMA stack that lets GPUs issue I/O requests directly using atomic operations and the SIMT execution model, and deEngine, which decomposes AFA tasks such as access control and metadata persistence into each SSD firmware. This produces a complete CPU-bypass path while preserving AFA semantics, yielding 3.2 times higher I/O throughput and 31.1 percent shorter application execution times than prior AFA systems.

What carries the argument

GNoR, the GPU-centric NVMe over RDMA stack that orchestrates I/O with atomic operations under the SIMT model, together with deEngine, the decentralized AFA engine placed inside SSD firmware.

If this is right

  • GPU applications gain direct use of remote AFA bandwidth without CPU orchestration costs.
  • I/O throughput rises by a measured factor of 3.2 compared with current CPU-centric AFA designs.
  • End-to-end application run times fall by 31.1 percent under the same workloads.
  • AFA-level guarantees remain available even though the CPU is removed from the I/O path.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same CPU-bypass pattern could be tested on other accelerators that currently route storage through a host CPU.
  • Clusters built around many GPUs might reduce their total CPU count if storage management moves entirely into the devices.
  • Further AFA features could be pushed into SSD firmware to test whether additional performance headroom appears.

Load-bearing premise

Essential AFA functions such as access control and metadata persistence can be decomposed and placed inside SSD firmware while keeping correctness and low overhead in a direct GPU-to-SSD path.

What would settle it

A measurement showing that access-control logic moved into SSD firmware either allows unauthorized access or adds latency that cancels the reported throughput gains would disprove the central claim.

Figures

Figures reproduced from arXiv: 2606.04908 by Chen Tian, Chenying Huan, Guoci Chen, Jie Zhang, Junrong Zhu, Mao Bo, Shengwen Liang, Shushu Yi, Wenbo Wu.

Figure 1
Figure 1. Figure 1: I/O path comparison of different GPU-AFA systems. provide fault tolerance for long-term data. For instance, the training corpus of LLMs has reached PB scale, which is per￾sistently stored on remote AFA and shared across multi￾ple GPU clients [14, 35, 47, 78]. Moreover, LLM training frequently generates checkpoints (including intermediate model weights and optimizer states), which can amount to tens of TBs … view at source ↗
Figure 2
Figure 2. Figure 2: Architectures of AFA and SSD. failures; (4) High performance: These datasets are frequently accessed by GPU during computation, making I/O perfor￾mance critical. For example, training processes repeatedly load the corpus for computation, while inference workloads demand low-latency access to shared data (e.g., KV cache). 2.2 All-Flash Array and SSD Architecture All-flash array. Due to the stringent storage… view at source ↗
Figure 3
Figure 3. Figure 3: Overview of GNStor. Challenge 1). GNoR is built from the ground up to exploit the massive parallelism of GPU architecture. Specifically, GNoR remains non-I/O-critical tasks and data structures (e.g., keep-alive handling and NVMe admin queues) on the CPU, as they are rarely called and have a minor impact on steady-state performance. In contrast, GNoR migrates I/O-critical components (e.g., NVMe I/O queues a… view at source ↗
Figure 4
Figure 4. Figure 4: Initialization and I/O procedures of channel. it also notifies the daemon via RPC. The daemon then up￾dates volume permission table on SSDs with customized VOLUME DELETE/CHMOD command and then acknowledges the client. GNStor assumes all clients in the GPU-AFA sys￾tem are trusted (e.g., in private clusters). Access control is primarily designed to support data sharing with consistency (i.e., accessing corre… view at source ↗
Figure 6
Figure 6. Figure 6: Merged FTL mapping table in deEngine. completely eliminates CPU intervention in I/O path, thereby achieving higher performance. Access control. As shown in [PITH_FULL_IMAGE:figures/full_fig_p007_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Illustration of batched I/O. critical metadata can be reliably recovered after system re￾boot. In GNStor, since AFA-level mapping tables have been integrated into the SSD-resident FTL, they naturally benefit from SSD-internal persistence and recovery mechanisms. This design eliminates the need for additional logging or checkpointing in the AFA layer. When a GPU client recovers or migrates, it can re-establ… view at source ↗
Figure 9
Figure 9. Figure 9: Throughput comparison on microbenchmarks. SSD/CPU-core ratio in commercial AFA products [13]. For real-world applications, we choose tensor computing, data pre-processing, graph analytics, and LLM training (cf [PITH_FULL_IMAGE:figures/full_fig_p009_9.png] view at source ↗
Figure 12
Figure 12. Figure 12: Scalability test with different numbers of SSDs. 4KB-Rd 4KB-Wr 64KB-Rd 64KB-Wr 0 4 8 1 2 1 6 (a) Ban dwi dth . B a n d wi d t h ( G B / s ) GD GD+deE n gi n e GN Stor 4KB-Rd 4KB-Wr 64KB-Rd 64KB-Wr 0 1 00 200 300 (b) Laten cy. A v g . l a t e n c y ( u s ) [PITH_FULL_IMAGE:figures/full_fig_p010_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: Ablation analysis. gains limited benefits in multi-client scenarios, even with extra CPU threads. For example, it achieves only 4.4 GB/s and 4.1 GB/s read and write throughput in 64 KB tests. This can be attributed to its CPU-centric design, in which the CPU-GPU interaction and memory copy overhead become the performance bottleneck. GD is more scalable than Basic, thanks to its peer-to-peer data transfer … view at source ↗
Figure 11
Figure 11. Figure 11: Scalability test with different numbers of clients. GD enables data zero-copy between GPU and NIC, avoiding the time-consuming detour to host memory. GNStor further reduces read and write latency by 35.7% and 39.8%, thanks to our fully CPU-bypass design, which paves the shortest I/O path between GPU and AFA. 5.3 Scalability Test Different numbers of clients. We further measure the scalability of different… view at source ↗
Figure 14
Figure 14. Figure 14: Tensor computing. Basi c GDGN Stor 0 1 0 20 30 40 50 60 Read Wri te Compu te T i m e ( s ) (b) E xec. time. Basi c GDGN Stor 0 400 800 1 200 1 600 T h r o u g h p u t ( i m a g e s / s ) (a) Th rou gh pu t [PITH_FULL_IMAGE:figures/full_fig_p011_14.png] view at source ↗
Figure 17
Figure 17. Figure 17: GPT-2 training. trains 50 steps (Compute), and then writes back the check￾point (including intermediate model weights and optimizer states, Checkpoint). Training datasets are cached in local host memory for fast loading. As shown in [PITH_FULL_IMAGE:figures/full_fig_p012_17.png] view at source ↗
read the original abstract

GPU has become the leading computing device for a wide range of data-intensive applications, which tightly collaborates with remote all-flash array (AFA) to accommodate ever-expanding datasets, facilitate multi-client data sharing, and guarantee fault tolerance. Although GPU is the center of computation, all I/O processes in existing GPU-AFA systems are still CPU-centric. CPU orchestrates remote I/O requests and executes a centralized AFA engine to take charge of AFA-level functionalities (e.g., access control and metadata persistence). This design disparity suffers from substantial CPU-GPU interaction overhead and I/O traffic amplification, compromising end-to-end I/O performance. In this work, we present \emph{GNStor}, a GPU-native AFA system that enables GPU to directly access remote AFA without CPU intervention in the I/O path, thereby fully exploiting the performance of AFA. Specifically, GNStor first proposes a GPU-centric NVMe over RDMA (NoR) software stack (named \emph{GNoR}), paving a fast path for GPUs to directly initiate NoR I/O requests to SSDs within remote AFA. GNoR employs an atomic-operation-based I/O orchestration design and follows the single-instruction-multiple-thread (SIMT) execution model of GPU, fully exploiting the massive parallelism of GPU architectures. To facilitate essential AFA functionalities in a CPU-bypass I/O path, GNStor further designs \emph{deEngine}, a decentralized AFA engine that seamlessly decomposes and integrates AFA-level tasks into each SSD firmware, thereby achieving efficient AFA access at low cost. Evaluation results show that GNStor achieves 3.2$\times$ higher I/O throughput and reduces application execution time by 31.1\%, compared to state-of-the-art AFA systems.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 0 minor

Summary. The paper presents GNStor, a GPU-native remote all-flash array (AFA) design that enables direct GPU-initiated I/O to remote SSDs without CPU intervention in the data path. It introduces GNoR, a GPU-centric NVMe over RDMA software stack using atomic operations and SIMT execution, and deEngine, a decentralized AFA engine that decomposes tasks such as access control and metadata persistence into per-SSD firmware. The central claim is that this CPU-bypass architecture delivers 3.2× higher I/O throughput and reduces application execution time by 31.1% versus state-of-the-art AFA systems.

Significance. If the performance numbers and correctness of the decentralized engine hold under realistic multi-client workloads, the work would represent a meaningful shift from CPU-orchestrated to GPU-direct remote storage for data-intensive GPU applications, potentially reducing interaction overhead and traffic amplification in GPU-AFA co-designs.

major comments (2)
  1. [Abstract / Evaluation] Abstract and Evaluation section: The specific claims of 3.2× throughput improvement and 31.1% execution-time reduction are stated without any description of experimental setup, baselines, workloads, hardware configuration, or error bars. This absence makes the central performance result unverifiable from the provided text and is load-bearing for the paper's contribution.
  2. [deEngine design] deEngine design (architecture section): The claim that essential AFA functionalities including access control and metadata persistence can be fully decomposed and integrated into individual SSD firmware while preserving correctness in a CPU-bypass path lacks a concrete mechanism for cross-device atomicity, policy replication, or power-loss persistence. If these cannot be handled without races or hidden CPU fallbacks, the reported throughput gains are at risk.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive comments and the recommendation for major revision. We address each major comment point by point below and outline the changes we will make to strengthen the manuscript.

read point-by-point responses

  1. Referee: [Abstract / Evaluation] Abstract and Evaluation section: The specific claims of 3.2× throughput improvement and 31.1% execution-time reduction are stated without any description of experimental setup, baselines, workloads, hardware configuration, or error bars. This absence makes the central performance result unverifiable from the provided text and is load-bearing for the paper's contribution.

    Authors: We agree that the abstract would benefit from a brief mention of the experimental context to improve immediate verifiability of the central claims. The full evaluation section provides details on the hardware platform (GPU and remote AFA configuration), baselines (state-of-the-art CPU-centric AFA systems), workloads, and reports results with error bars from repeated runs. In the revised version we will expand the abstract with a concise experimental overview and ensure the evaluation section opens with an explicit setup subsection. revision: yes

  2. Referee: [deEngine design] deEngine design (architecture section): The claim that essential AFA functionalities including access control and metadata persistence can be fully decomposed and integrated into individual SSD firmware while preserving correctness in a CPU-bypass path lacks a concrete mechanism for cross-device atomicity, policy replication, or power-loss persistence. If these cannot be handled without races or hidden CPU fallbacks, the reported throughput gains are at risk.

    Authors: We acknowledge that the current architecture description would be strengthened by additional concrete mechanisms. The deEngine design relies on per-SSD firmware extensions coordinated via GPU-initiated RDMA atomics, but explicit details on cross-device atomicity (e.g., distributed locking), policy replication, and power-loss persistence (e.g., journaling) are not fully elaborated. We will add a dedicated subsection in the revised architecture section that specifies these mechanisms, discusses potential race conditions, and clarifies that no hidden CPU fallbacks are used in the data path. revision: yes

Circularity Check

0 steps flagged

No circularity: systems design with external evaluation

full rationale

The paper presents an architectural design (GNoR stack and deEngine decomposition) and reports measured throughput gains from implementation and benchmarking. No equations, fitted parameters, or predictions appear; performance claims rest on described hardware/software changes evaluated against external baselines rather than any self-referential reduction or self-citation chain. The central claim is therefore independent of its own inputs.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 2 invented entities

This is an engineering systems paper introducing new software components with no mathematical free parameters, axioms, or invented physical entities; the design rests on standard assumptions about NVMe, RDMA, and SSD firmware capabilities.

invented entities (2)
  • GNoR no independent evidence
    purpose: GPU-centric NVMe over RDMA software stack for direct GPU I/O initiation
    New software stack proposed to enable CPU-bypass path
  • deEngine no independent evidence
    purpose: Decentralized AFA engine decomposed into SSD firmware
    New component to handle AFA functionalities without CPU

pith-pipeline@v0.9.1-grok · 5910 in / 1101 out tokens · 78728 ms · 2026-06-28T03:21:32.802334+00:00 · methodology

discussion (0)

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