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arxiv: 2606.18494 · v1 · pith:RZCDVRYFnew · submitted 2026-06-16 · 🪐 quant-ph

Towards an Optimally Distributed Quantum Fourier Transform Circuit

Zachary Vernec , Michael Silver , Hans-Arno Jacobsen This is my paper

Pith reviewed 2026-06-26 23:58 UTC · model grok-4.3

classification 🪐 quant-ph
keywords quantum Fourier transformcircuit partitioningdistributed quantum computinge-bit countgate packingquantum teleportationquantum hardware
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The pith

A gate-packing scheme partitions the quantum Fourier transform circuit using fewer entangled pairs than prior analytical or general methods.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper develops a partitioning approach for the quantum Fourier transform that splits the circuit across separate quantum processors while using quantum teleportation to connect them. It introduces optimal gate-packing to minimize the number of entangled qubit pairs, called e-bits, needed between processors. The new scheme is compared directly to earlier analytical partitions specific to the QFT and to outputs from general-purpose partitioning tools. The partitioned version is then run on quantum hardware to confirm it matches the original operation. A sympathetic reader would care because the QFT appears in many quantum algorithms, and lowering entanglement overhead could make distributed implementations more practical as systems scale.

Core claim

The authors present a partitioning scheme based on optimal gate-packing for the QFT that minimizes e-bit count while exactly preserving the unitary operation of the original circuit. This scheme is shown to require fewer e-bits than previous analytical partitioning methods designed for the QFT and than partitions generated by general-purpose circuit partitioning algorithms, with validation through implementation on quantum hardware.

What carries the argument

The optimal gate-packing partitioning scheme, which rearranges gates within the QFT to minimize cross-processor entanglements while keeping the overall unitary identical.

If this is right

  • Distributed QFT circuits require fewer e-bits than those produced by earlier analytical schemes.
  • The gate-packing partitions outperform those from general-purpose partitioning algorithms on the e-bit metric.
  • The partitioned QFT can be executed on quantum hardware without changing the implemented operation.
  • Lower e-bit counts directly reduce the entanglement generation cost between QPUs.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same packing logic could be tested on other subroutines that appear inside phase estimation or arithmetic circuits.
  • If e-bit savings scale with circuit size, the method might reduce the total entanglement resources needed for larger distributed algorithms.
  • Hardware validation on small instances leaves open whether the savings persist when noise and teleportation errors are included at scale.

Load-bearing premise

A gate-packing method can be made optimal for the QFT while exactly preserving the unitary operation of the original circuit.

What would settle it

A side-by-side count of e-bits required by the gate-packing partition versus prior analytical QFT partitions for a fixed circuit size, or a hardware run measuring output fidelity against the ideal QFT.

Figures

Figures reproduced from arXiv: 2606.18494 by Hans-Arno Jacobsen, Michael Silver, Zachary Vernec.

Figure 1
Figure 1. Figure 1: A state teleportation protocol (teledata) using starting and ending processes. The LHS uses a common circuit notation such as would be used [PITH_FULL_IMAGE:figures/full_fig_p004_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: A gate teleportation protocol (telegate) using starting and ending processes. The same diagrammatic notation is used on the left-hand side and [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: An example of gate packing the CX gate and the CZ gate, both with control qubit c and targeting qubits t1, t2 on the same QPU. On the left is the circuit that needs to be partitioned. In the middle is the circuit partition without gate packing, which requires two starting processes and therefore two e-bits. On the right is an equivalent partition where the CX and CZ gates are packed so that a single starti… view at source ↗
Figure 4
Figure 4. Figure 4: An example of a detached gate. A non-local [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: The traditional circuit for the quantum Fourier transform on 6 qubits, where the subscript k [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Semi-classical QFT circuit on 6 qubits. Note that the double lines represent classical information propagation and classical control. [PITH_FULL_IMAGE:figures/full_fig_p006_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Yimsiriwattana and Lomonaco Jr’s distributed QFT circuit on 6 qubits across 3 uneven-sized QPUs, drawn using the starting and ending process [PITH_FULL_IMAGE:figures/full_fig_p006_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: The linear topology QFT on 6 qubits, as diagrammed in [34]. Note the angles of the [PITH_FULL_IMAGE:figures/full_fig_p006_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: The linear topology QFT on 6 qubits, using teledata-based circuit distribution. Recall that the double snake arrows represent state teleportation. [PITH_FULL_IMAGE:figures/full_fig_p006_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Alternate view of the QFT circuit, where the designation of [PITH_FULL_IMAGE:figures/full_fig_p009_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Proposed circuit distributed for QFT that includes gate packing. Note that for simplicity, the [PITH_FULL_IMAGE:figures/full_fig_p010_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: (a) K6, the interaction graph for a 6-qubit QFT. Node colours correspond to QPU assignment, but are irrelevant for this (local) interaction graph. (b) K1,2,3, the non-local interaction graph for a 6-qubit distributed QFT on QPUs of sizes 1, 2, 3. An arbitrary assignment of root and target qubits is given by edge directions. (c) K1,2 ∪ K1,3 ∪ K2,3, the constraint graph for a 6-qubit distributed QFT on QPUs… view at source ↗
Figure 13
Figure 13. Figure 13: A 6-qubit (simplified) QFT circuit implemented using gate packing and a maximum number of detached gates. [PITH_FULL_IMAGE:figures/full_fig_p012_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: Typical e-bit counts for partitioning various QFT sizes into 2 and 4 QPUs. [PITH_FULL_IMAGE:figures/full_fig_p013_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: Typical time for partitioning various QFT sizes into 2 and 4 QPUs on a laptop. [PITH_FULL_IMAGE:figures/full_fig_p013_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: A layout of a partitioned QFT across a virtually split backend. The [PITH_FULL_IMAGE:figures/full_fig_p015_16.png] view at source ↗
Figure 18
Figure 18. Figure 18: Average fidelities of the naively partitioned QFT and our gate [PITH_FULL_IMAGE:figures/full_fig_p016_18.png] view at source ↗
Figure 19
Figure 19. Figure 19: These data are from the same experiment as for aver￾age fidelities ( [PITH_FULL_IMAGE:figures/full_fig_p016_19.png] view at source ↗
Figure 20
Figure 20. Figure 20: Output fidelities of the gate-packed partitioned QFT for input [PITH_FULL_IMAGE:figures/full_fig_p017_20.png] view at source ↗
Figure 21
Figure 21. Figure 21: Time to compute the average fidelity of the naively partitioned [PITH_FULL_IMAGE:figures/full_fig_p017_21.png] view at source ↗
read the original abstract

A promising avenue for scaling quantum computing is to connect quantum processing units (QPUs) by generating entanglement between them. This requires circuit partitioning: partially rewriting quantum circuits to run on a distributed quantum system using quantum teleportation protocols, while preserving the unitary operation implemented by the circuit. The key metric to minimize when partitioning is the e-bit count, defined as the number of maximally entangled qubit pairs that must be generated between QPUs. We focus on partitioning the quantum Fourier transform (QFT) circuit, which is widely used as a subroutine in quantum algorithms such as quantum phase estimation and arithmetic circuits. Specifically, we present a partitioning scheme based on optimal gate-packing, compare it against prior analytical partitioning schemes for the QFT, and evaluate it against partitions produced by general-purpose circuit partitioning algorithms. We further validate our approach by implementing the partitioned circuit on quantum hardware.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The manuscript presents a partitioning scheme for the quantum Fourier transform (QFT) circuit based on optimal gate-packing for distributed quantum systems. The scheme minimizes the e-bit count (number of maximally entangled pairs between QPUs) while preserving the original unitary. It compares the scheme to prior analytical QFT partitioning methods and to outputs from general-purpose circuit partitioning algorithms, and reports hardware validation via implementation on quantum hardware.

Significance. If the optimality claim, comparisons, and hardware results hold with quantitative improvements, the work would offer a concrete method for distributing an important quantum subroutine, supporting multi-QPU scaling. The explicit focus on e-bit minimization and the dual comparison (analytical + general-purpose) plus hardware step are positive features that could inform practical distributed quantum algorithm design.

major comments (2)
  1. [Abstract] Abstract: the central claim that the gate-packing scheme is 'optimal' and yields lower e-bit counts than prior analytical schemes is not accompanied by any definition of optimality, complexity analysis, or quantitative comparison data in the visible text; without these, it is impossible to verify whether the reported reductions are load-bearing or merely heuristic improvements.
  2. [Abstract] Abstract: the hardware validation is stated to 'further validate our approach,' yet no metrics (e.g., fidelity, e-bit overhead measured on device, circuit depth after partitioning) or device details are supplied, leaving the preservation of the unitary and practical advantage uncheckable.
minor comments (1)
  1. [Abstract] Abstract: the phrase 'optimal gate-packing' is used without a forward reference to the section that defines the packing objective or the algorithm; adding such a pointer would improve readability.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for their comments. We address each major comment below.

read point-by-point responses

  1. Referee: [Abstract] Abstract: the central claim that the gate-packing scheme is 'optimal' and yields lower e-bit counts than prior analytical schemes is not accompanied by any definition of optimality, complexity analysis, or quantitative comparison data in the visible text; without these, it is impossible to verify whether the reported reductions are load-bearing or merely heuristic improvements.

    Authors: The manuscript defines optimality as the gate-packing scheme achieving the minimum e-bit count for a given QPU count while exactly preserving the QFT unitary. The full text supplies the formal definition, complexity analysis of the packing procedure, and quantitative e-bit comparisons versus prior analytical QFT partitions and general-purpose algorithms. To render the abstract self-contained, we will revise it to state the optimality criterion and report the observed e-bit reductions. revision: yes

  2. Referee: [Abstract] Abstract: the hardware validation is stated to 'further validate our approach,' yet no metrics (e.g., fidelity, e-bit overhead measured on device, circuit depth after partitioning) or device details are supplied, leaving the preservation of the unitary and practical advantage uncheckable.

    Authors: The experimental section of the manuscript reports the specific quantum device, measured fidelities, circuit depths after partitioning, and explicit verification that the distributed implementation preserves the original unitary. We agree the abstract would benefit from inclusion of these key metrics and device information. We will revise the abstract accordingly. revision: yes

Circularity Check

0 steps flagged

No significant circularity

full rationale

The paper presents a gate-packing partitioning scheme for the QFT, compares it to prior analytical schemes and general-purpose algorithms, and validates via hardware implementation. The central claim is the scheme itself plus empirical comparisons; the unitary-preservation requirement is stated explicitly as a design constraint rather than derived. No self-definitional steps, fitted inputs renamed as predictions, or load-bearing self-citations appear in the derivation chain. The work is self-contained against external benchmarks (prior schemes, general algorithms, hardware runs).

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Abstract supplies no information on free parameters, axioms, or invented entities.

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discussion (0)

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Reference graph

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