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Composable and Modular Code Generation in MLIR: A Structured and Retargetable Approach to Tensor Compiler Construction

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arxiv 2202.03293 v1 pith:QLD5RZLM submitted 2022-02-07 cs.PL

Nicolas Vasilache , Oleksandr Zinenko , Aart J.C. Bik , Mahesh Ravishankar , Thomas Raoux , Alexander Belyaev , Matthias Springer , Tobias Gysi
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Diego Caballero Stephan Herhut Stella Laurenzo Albert Cohen
This is my paper · ORCID
classification cs.PL
keywords approachcompilerconstructiontensorcodecompilersdesigninfrastructure
verification ladder T0 review T1 audit T2 compute T3 formal
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Despite significant investment in software infrastructure, machine learning systems, runtimes and compilers do not compose properly. We propose a new design aiming at providing unprecedented degrees of modularity, composability and genericity. This paper discusses a structured approach to the construction of domain-specific code generators for tensor compilers, with the stated goal of improving the productivity of both compiler engineers and end-users. The approach leverages the natural structure of tensor algebra. It has been the main driver for the design of progressive lowering paths in \MLIR. The proposed abstractions and transformations span data structures and control flow with both functional (SSA form) and imperative (side-effecting) semantics. We discuss the implications of this infrastructure on compiler construction and present preliminary experimental results.

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Cited by 4 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. E-Graphs as a Persistent Compiler Abstraction

    cs.PL 2026-02 conditional novelty 7.0 of 10

    E-graphs become first-class compiler IR via the eqsat dialect, enabling persistent equality saturation; a partial Herbie reimplementation matches accuracy but is ~400× slower.

  2. Correct but Slow: An Empirical Study of the GPU Kernel Evaluation Gap in Modern Domain-Specific Languages

    cs.SE 2026-07 unverdicted novelty 6.0 of 10

    Correctness-only evaluation of Triton and TileLang kernels admits slowdowns over 300× versus library baselines; library-relative efficiency and roofline utilization flag all such failures in a 22-kernel suite.

  3. A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions

    cs.PL 2025-02 conditional novelty 6.0 of 10

    A multi-level MLIR/xDSL backend for the Snitch RISC-V accelerator reaches up to 95% FPU utilization on micro-kernels and 90% when lowered from linalg, without register spilling.

  4. Nova: An End-to-End MLIR Compiler for Deep Learning

    cs.AI 2026-07 conditional novelty 5.0 of 10

    A search-free MLIR compiler that fuses whole training steps outperforms PyTorch by up to ~10% and cuts memory by up to 29%, fitting 144M-parameter MLPs on a 12 GB GPU.

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