Pith. sign in

REVIEW 2 cited by

HybridTier: an Adaptive and Lightweight CXL-Memory Tiering System

Not yet reviewed by Pith; the record is open.

This paper has not been read by Pith yet. Machine review is queued; the pith claim, tier, and objections will appear here once it completes.

SPECIMEN: schema-true, not a live event

T0 review · schema-true

One-sentence machine reading of the paper's core claim.

pith:XXXXXXXX · record.json · timestamp

arxiv 2312.04789 v2 pith:RDGJCAUL submitted 2023-12-08 cs.DC cs.OS

classification cs.DCcs.OS
keywords memorydatahybridtiertieringoverheadcachehotnesslightweight
verification ladder T0 review T1 audit T2 compute T3 formal
0 comments
abstract

Modern workloads are demanding increasingly larger memory capacity. Compute Express Link (CXL)-based memory tiering has emerged as a promising solution for addressing this problem by utilizing traditional DRAM alongside slow-tier CXL memory devices. We analyze prior tiering systems and observe two challenges for high-performance memory tiering: adapting to skewed but dynamically varying data hotness distributions while minimizing memory and cache overhead due to tiering. To address these challenges, we propose HybridTier, an adaptive and lightweight tiering system for CXL memory. HybridTier tracks both long-term data access frequency and short-term access momentum \emph{simultaneously} to accurately capture and adapt to shifting hotness distributions. HybridTier reduces the metadata memory overhead by tracking data accesses \emph{probabilistically}, obtaining higher memory efficiency by trading off a small amount of tracking inaccuracy that has a negligible impact on application performance. To reduce cache overhead, HybridTier uses lightweight data structures that optimize for data locality to track data hotness. Our evaluations show that HybridTier outperforms prior systems by up to $91\%$ ($19\%$ geomean), incurring $2.0-7.8\times$ less memory overhead and $1.7-3.5\times$ less cache misses.

Discussion (0). Continue with ORCID to comment.

Forward citations

Cited by 2 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. CXL-Interference: Analysis and Characterization in Modern Computer Systems

    cs.AR 2024-11 conditional novelty 6.0 of 10

    CXL memory traffic, especially non-temporal stores, can degrade concurrent DRAM and SSD bandwidth by up to 93.2%, and CPU quota or MBA regulation can restore about 99% of DRAM bandwidth.

  2. Next-Gen Computing Systems with Compute Express Link: a Comprehensive Survey

    cs.DC 2024-12 conditional novelty 4.0 of 10

    A structured survey of CXL-based computing system research, organized by memory expansion, unified memory, and distributed memory pooling and sharing.

Pith tools