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SpiNNaker2: A Large-Scale Neuromorphic System for Event-Based and Asynchronous Machine Learning

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arxiv 2401.04491 v1 pith:5ZVNK37U submitted 2024-01-09 cs.ET cs.LGcs.NE

Hector A. Gonzalez , Jiaxin Huang , Florian Kelber , Khaleelulla Khan Nazeer , Tim Langer , Chen Liu , Matthias Lohrmann , Amirhossein Rostami
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Mark Schöne Bernhard Vogginger Timo C. Wunderlich Yexin Yan Mahmoud Akl Christian Mayr
This is my paper · ORCID
classification cs.ETcs.LGcs.NE
keywords learningsystemsmachinespinnaker2applicationsevent-basedasynchronouscomputational
verification ladder T0 review T1 audit T2 compute T3 formal
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The joint progress of artificial neural networks (ANNs) and domain specific hardware accelerators such as GPUs and TPUs took over many domains of machine learning research. This development is accompanied by a rapid growth of the required computational demands for larger models and more data. Concurrently, emerging properties of foundation models such as in-context learning drive new opportunities for machine learning applications. However, the computational cost of such applications is a limiting factor of the technology in data centers, and more importantly in mobile devices and edge systems. To mediate the energy footprint and non-trivial latency of contemporary systems, neuromorphic computing systems deeply integrate computational principles of neurobiological systems by leveraging low-power analog and digital technologies. SpiNNaker2 is a digital neuromorphic chip developed for scalable machine learning. The event-based and asynchronous design of SpiNNaker2 allows the composition of large-scale systems involving thousands of chips. This work features the operating principles of SpiNNaker2 systems, outlining the prototype of novel machine learning applications. These applications range from ANNs over bio-inspired spiking neural networks to generalized event-based neural networks. With the successful development and deployment of SpiNNaker2, we aim to facilitate the advancement of event-based and asynchronous algorithms for future generations of machine learning systems.

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Cited by 8 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. The Sparsity Tax: Weight Sparsity Trade-offs in Event-Driven SIMD and SIMT Neuromorphic Cores

    cs.AR 2026-07 conditional novelty 6.0 of 10

    A silicon-level comparison of three neuromorphic core variants shows that bitmap-gated SIMD saves energy but not time, while a SIMT core with per-PE address generation cuts both time and energy at high sparsity, with ...

  2. Robust PnP on a Neuromorphic Processor for Object Pose Estimation

    cs.CV 2026-07 conditional novelty 6.0 of 10

    A robust PnP solver (NeuroPnP) is reformulated as an energy-minimization problem that runs on Intel Loihi 2, achieving roughly 1% of a CPU's power draw, with competitive accuracy in CPU simulation but lower accuracy o...

  3. Full Integer Arithmetic Online Training for Spiking Neural Networks

    cs.NE 2025-09 conditional novelty 6.0 of 10

    An integer-only, online training algorithm for spiking neural networks uses mixed-precision shadow weights and bit-shift operations to match full-precision accuracy with over 60% lower memory usage.

  4. Hardware-Aware Fine-Tuning of Spiking Q-Networks on the SpiNNaker2 Neuromorphic Platform

    cs.LG 2025-07 conditional novelty 6.0 of 10

    A quantized spiking Q-network deployed on SpiNNaker2 matches a GPU on CartPole and Acrobot while using 24x to 32x less energy per episode.

  5. An End-to-End DNN Inference Framework for the SpiNNaker2 Neuromorphic MPSoC

    cs.LG 2025-07 conditional novelty 5.0 of 10

    An extension of OctopuScheduler lets a single SpiNNaker2 chip run multi-layer DNNs end-to-end from PyTorch models with 8-bit quantization.

  6. Spiking Neural Networks for SAR Interferometric Phase Unwrapping: A Theoretical Framework for Energy-Efficient Processing

    cs.NE 2025-06 reject novelty 5.0 of 10

    The paper proposes the first spiking neural network framework for SAR phase unwrapping, with encoding schemes, an architecture, and theoretical complexity and convergence claims, but no experiments.

  7. FeNN: A RISC-V vector processor for Spiking Neural Network acceleration

    cs.NE 2025-06 conditional novelty 5.0 of 10

    A single FeNN FPGA vector core can classify spoken digits as accurately as a 32-bit floating-point SNN simulator while running faster and using less energy than an embedded GPU and a reported Loihi baseline.

  8. Beyond Peak TOPS/W: A System-Level Perspective on Hybrid Digital, Analogue and Neuromorphic Computing

    cs.AR 2026-08 accept novelty 3.0 of 10

    Hybrid systems that mix digital control with physical accelerators should be judged by deployed-system metrics rather than isolated peak TOPS/W.

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