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Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS

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arxiv 2402.03289 v1 pith:6QPMTHOX submitted 2024-02-05 cs.LG cs.AIcs.AR

classification cs.LGcs.AIcs.AR
keywords codelanguagetransformercorrectdecodingfunctionallygenerationlarge
verification ladder T0 review T1 audit T2 compute T3 formal
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Existing large language models (LLMs) for register transfer level code generation face challenges like compilation failures and suboptimal power, performance, and area (PPA) efficiency. This is due to the lack of PPA awareness in conventional transformer decoding algorithms. In response, we present an automated transformer decoding algorithm that integrates Monte Carlo tree-search for lookahead, guiding the transformer to produce compilable, functionally correct, and PPA-optimized code. Empirical evaluation with a fine-tuned language model on RTL codesets shows that our proposed technique consistently generates functionally correct code compared to prompting-only methods and effectively addresses the PPA-unawareness drawback of naive large language models. For the largest design generated by the state-of-the-art LLM (16-bit adder), our technique can achieve a 31.8% improvement in the area-delay product.

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Forward citations

Cited by 3 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems

    cs.AR 2025-06 conditional novelty 6.0 of 10

    On three NIST crypto standards (AES, DSS, HMAC), Spec2RTL-Agent generates RTL via a multi-agent pipeline from pseudocode to Python to synthesizable C++, reporting 3/3 correct designs with about 4.3 human interventions...

  2. VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs

    cs.SE 2025-07 conditional novelty 5.0 of 10

    A multi-role LLM prompting framework with PPA-aware in-context learning reports 25/29 functional correctness on RTLLM and up to 88% power, 76% area, and 73% timing gains over its own baseline.

  3. Hardware Design and Security in the Era of Chiplets and LLMs

    cs.CR 2026-08 accept novelty 2.0 of 10

    A survey uniting chiplet-hardware security and LLM-driven EDA security that identifies a missing bridge: LLM-based security tools are not yet tailored to 2.5D/3D chiplet systems.

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