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Faster and shorter synthesis of Hamiltonian simulation circuits

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arxiv 2404.03280 v1 pith:ZWYC444Y submitted 2024-04-04 quant-ph cs.DM

classification quant-phcs.DM
keywords circuitsheuristicsdeptheitherentanglinggateshamiltonianquantum
verification ladder T0 review T1 audit T2 compute T3 formal
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We devise greedy heuristics tailored for synthesizing quantum circuits that implement a specified set of Pauli rotations. Our heuristics are designed to minimize either the count of entangling gates or the depth of entangling gates, and they can be adjusted to either maintain or loosen the ordering of rotations. We present benchmark results demonstrating a depth reduction of up to a factor of 4 compared to the current state-of-the-art heuristics for synthesizing Hamiltonian simulation circuits. We also show that these heuristics can be used to optimize generic quantum circuits by decomposing and resynthesizing them.

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Cited by 2 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Toward Minimum Graphic Parity Networks

    quant-ph 2025-09 conditional novelty 7.0 of 10

    The minimum size of a graphic parity network for a connected graph is at least m+n-1, rising to m+Omega(n^1.5) for graphs with no short cycles, and a randomized construction achieves m+O(n^1.5 sqrt(log n)).

  2. Quantum Compiler Design for Qubit Mapping and Routing: A Cross-Architectural Survey of Superconducting, Trapped-Ion, and Neutral Atom Systems

    quant-ph 2025-05 conditional novelty 4.0 of 10

    A cross-architectural survey that categorizes qubit mapping and routing compilers for superconducting, trapped-ion, and neutral atom quantum hardware.

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