REVIEW 2 cited by
Are LLMs Any Good for High-Level Synthesis?
Not yet reviewed by Pith; the record is open.
This paper has not been read by Pith yet. Machine review is queued; the pith claim, tier, and objections will appear here once it completes.
SPECIMEN: schema-true, not a live event
T0 review · schema-true
One-sentence machine reading of the paper's core claim.
pith:XXXXXXXX · record.json · timestamp
Signed reviews
read the original abstract
The increasing complexity and demand for faster, energy-efficient hardware designs necessitate innovative High-Level Synthesis (HLS) methodologies. This paper explores the potential of Large Language Models (LLMs) to streamline or replace the HLS process, leveraging their ability to understand natural language specifications and refactor code. We survey the current research and conduct experiments comparing Verilog designs generated by a standard HLS tool (Vitis HLS) with those produced by LLMs translating C code or natural language specifications. Our evaluation focuses on quantifying the impact on performance, power, and resource utilization, providing an assessment of the efficiency of LLM-based approaches. This study aims to illuminate the role of LLMs in HLS, identifying promising directions for optimized hardware design in applications such as AI acceleration, embedded systems, and high-performance computing.
Forward citations
Cited by 2 Pith papers
-
C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap
An LLM-based, feedback-driven pipeline rewrites generic C programs into HLS-synthesizable C, succeeding on most but not all of ten real-world benchmarks.
-
Advancing AI-assisted Hardware Design with Hierarchical Decentralized Training and Personalized Inference-Time Optimization
A two-stage framework of hierarchical decentralized training plus personalized test-time optimization raises LLM hardware generation accuracy and speed in HLS and Qiskit benchmarks.
Discussion (0). Continue with ORCID to comment.