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arxiv: 2409.03993 · v1 · submitted 2024-09-06 · ❄️ cond-mat.mes-hall · quant-ph

CMOS compatibility of semiconductor spin qubits

Nard Dumoulin Stuyck , Andre Saraiva , Will Gilbert , Jesus Cifuentes Pardo , Ruoyu Li , Christopher C. Escott , Kristiaan De Greve , Sorin Voinigescu
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David J. Reilly Andrew S. Dzurak
This is my paper

Pith reviewed 2026-05-23 21:11 UTC · model grok-4.3

classification ❄️ cond-mat.mes-hall quant-ph
keywords semiconductor spin qubitsCMOS compatibilityfault-tolerant quantum computingVLSI integrationsilicon quantum devicesquantum hardware scaling
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The pith

Semiconductor spin qubits can leverage existing CMOS fabrication infrastructure to reach the scale needed for fault-tolerant quantum computing.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper examines how semiconductor spin qubits can be made compatible with CMOS technology used in classical chips. It argues that this compatibility gives spin qubits an edge in scaling up to the millions of qubits required for useful fault-tolerant quantum computing. By reviewing the overlap with VLSI principles, the authors highlight where spin qubit designs match industry practices and where adjustments are needed. This review aims to guide collaboration between qubit developers and semiconductor manufacturers toward industrial production of quantum processors.

Core claim

Semiconductor spin qubits possess unique advantages in CMOS compatibility that position them as leading candidates for large-scale fault-tolerant quantum computing. The compatibility spans from using silicon wafers as substrates to co-integrating qubits with control electronics, allowing extrapolation from current quantum processors to future systems that meet FTQC requirements through established semiconductor industry methods.

What carries the argument

CMOS compatibility, ranging from wafer substrate use to full co-integration with high-yield electronics for qubit control.

Load-bearing premise

The integration challenges already solved by the semiconductor industry for classical VLSI systems can be directly retrofitted to qubit systems without introducing new quantum-specific barriers at scale.

What would settle it

Demonstration that spin qubit coherence times or gate fidelities drop significantly when fabricated using standard advanced CMOS processes at industrial scales would challenge the compatibility claim.

read the original abstract

Several domains of society will be disrupted once millions of high-quality qubits can be brought together to perform fault-tolerant quantum computing (FTQC). All quantum computing hardware available today is many orders of magnitude removed from the requirements for FTQC. The intimidating challenges associated with integrating such complex systems have already been addressed by the semiconductor industry -hence many qubit makers have retrofitted their technology to be CMOS-compatible. This compatibility, however, can have varying degrees ranging from the mere ability to fabricate qubits using a silicon wafer as a substrate, all the way to the co-integration of qubits with high-yield, low-power advanced electronics to control these qubits. Extrapolating the evolution of quantum processors to future systems, semiconductor spin qubits have unique advantages in this respect, making them one of the most serious contenders for large-scale FTQC. In this review, we focus on the overlap between state-of-the-art semiconductor spin qubit systems and CMOS industry Very Large-Scale Integration (VLSI) principles. We identify the main differences in spin qubit operation, material, and system requirements compared to well-established CMOS industry practices. As key players in the field are looking to collaborate with CMOS industry partners, this review serves to accelerate R&D towards the industrial scale production of FTQC processors.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. This review argues that semiconductor spin qubits possess unique advantages for large-scale fault-tolerant quantum computing (FTQC) stemming from their compatibility with CMOS VLSI principles. It surveys the spectrum of compatibility (from silicon-substrate fabrication to co-integration with control electronics), contrasts spin-qubit materials, control, and yield requirements with established CMOS practices, and identifies overlaps to accelerate industrial collaboration.

Significance. If the mapping of overlaps and gaps is accurate, the review could usefully inform qubit-CMOS co-design efforts. However, the central claim that spin qubits are thereby 'one of the most serious contenders' for FTQC rests on an untested extrapolation that classical CMOS solutions can be retrofitted without introducing new quantum-specific barriers at scale; the manuscript supplies no quantitative scaling analysis or cited demonstrations of FTQC-relevant metrics under co-integrated control beyond small arrays.

major comments (2)
  1. [Abstract] Abstract: the assertion of 'unique advantages' that make spin qubits 'one of the most serious contenders for large-scale FTQC' is load-bearing yet unsupported by any comparative scaling analysis or cited data on fidelity/coherence under co-integrated CMOS at >1000-qubit scale.
  2. [Introduction / overlap analysis sections] The review identifies differences in materials, control, and yield but provides no quantitative assessment of whether these differences introduce quantum-specific limits (e.g., charge-noise coupling from integrated CMOS or crosstalk at high density) that cannot be solved by existing industry processes; this assumption underpins the 'serious contender' conclusion.
minor comments (2)
  1. Notation for compatibility levels (substrate-only vs. full co-integration) is introduced but not used consistently when citing specific device demonstrations.
  2. Several cited works on classical CMOS yield statistics lack page or section references, making it difficult to verify the claimed parallels.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the detailed and constructive report. The comments correctly identify that our review is prospective and does not contain new quantitative scaling data at FTQC-relevant scales. We have revised the manuscript to qualify the central claims more precisely, to state the assumptions explicitly, and to highlight the absence of large-scale co-integrated demonstrations. These changes do not alter the review's scope or its utility for mapping CMOS-qubit overlaps.

read point-by-point responses

  1. Referee: [Abstract] Abstract: the assertion of 'unique advantages' that make spin qubits 'one of the most serious contenders for large-scale FTQC' is load-bearing yet unsupported by any comparative scaling analysis or cited data on fidelity/coherence under co-integrated CMOS at >1000-qubit scale.

    Authors: We agree that the original abstract language extrapolated beyond the data presented. The review surveys compatibility overlaps and differences but contains no scaling analysis or >1000-qubit co-integrated metrics, as none exist in the literature. We have revised the abstract to replace the phrase 'one of the most serious contenders for large-scale FTQC' with 'offer a promising route toward large-scale FTQC that merits industrial-scale investigation,' and we have added an explicit caveat that current demonstrations remain at small arrays. This revision aligns the abstract with the manuscript's actual content. revision: yes

  2. Referee: [Introduction / overlap analysis sections] The review identifies differences in materials, control, and yield but provides no quantitative assessment of whether these differences introduce quantum-specific limits (e.g., charge-noise coupling from integrated CMOS or crosstalk at high density) that cannot be solved by existing industry processes; this assumption underpins the 'serious contender' conclusion.

    Authors: The manuscript is a review whose stated goal is to map overlaps between spin-qubit requirements and CMOS VLSI practices to facilitate collaboration; it does not claim to perform quantitative limit analysis. We acknowledge that the text does not evaluate whether identified differences create insurmountable quantum-specific barriers. In the revised version we have inserted a dedicated paragraph in the introduction that (i) states the assumption that industry processes can address the differences, (ii) notes the current absence of experimental data on charge-noise coupling or high-density crosstalk under co-integration, and (iii) identifies these topics as open research questions. This addition makes the underlying assumption transparent without expanding the review into a quantitative study. revision: yes

Circularity Check

0 steps flagged

Review paper aggregates external sources with no internal derivation chain

full rationale

This is a review paper that surveys overlaps between spin-qubit systems and CMOS VLSI practices, identifies differences, and discusses collaboration opportunities. The abstract and provided text contain no equations, fitted parameters, predictions, or self-citations used as load-bearing premises for a new result. The central claim is an assessment of advantages drawn from external literature rather than a derivation that reduces to its own inputs. No circular steps are present.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

This review paper does not introduce new free parameters, axioms, or invented entities. It relies on the existing body of literature on semiconductor spin qubits and CMOS technology.

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Forward citations

Cited by 4 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. Spin Qubit Leapfrogging: Dynamics of shuttling electrons on top of another

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    Mobile spin qubits in silicon can leapfrog over occupied dots by exploiting low valley splitting, enabling new connectivity routes and SWAP^γ entangling gates.

  2. Two-dimensional Si spin qubit arrays with multilevel interconnects

    quant-ph 2025-02 unverdicted novelty 7.0

    Demonstration of an extendable 2D silicon spin qubit array with multilevel interconnects enabling high-fidelity exchange-only qubits and defect-tolerant reconfigurability.

  3. Gate Stack Engineering for High-Mobility and Low-Noise SiMOS Quantum Devices

    cond-mat.mes-hall 2026-03 unverdicted novelty 4.0

    Raising the atomic-layer deposition temperature of Al2O3 and using HfO2 or poly-Si gates in SiMOS devices correlates with higher mobility and lower charge noise, yielding more stable quantum dots.

  4. Device/circuit simulations of silicon spin qubits based on a gate-all-around transistor

    cond-mat.mes-hall 2025-12 unverdicted novelty 4.0

    TCAD device simulations and SPICE circuit simulations indicate that spin-dependent charge distributions in a GAA transistor produce distinguishable currents that a conventional CMOS sense amplifier can detect when vol...

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