IP-CaT jointly optimizes TLB and cache management for L1I prefetching via a translation prefetch buffer and trimodal replacement policy, yielding 8.7% geomean speedup over EPI across 105 server workloads.
Pattison, Srilatha Manne, Douglas M
8 Pith papers cite this work. Polarity classification is still indexing.
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Pith papers citing it
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UNVERDICTED 8representative citing papers
MIPSBLEED uncovers timing leaks in L1 data cache, L1 instruction cache, and execution engine of SMT-enabled MIPS processors and demonstrates a single-trace key recovery attack on elliptic curve cryptography.
DAE4HLS enables explicit decoupling of access and execute in HLS to unlock memory-level parallelism, delivering 10-79x speedups for complex workloads on commercial and dynamic HLS tools.
A microarchitecture-aware compiler for lattice surgery that exploits C-Phase commutativity to enable concurrent multi-target operations and dynamic event-driven scheduling, cutting execution time by up to 59.7 times versus standard baselines.
Lottery BP adds randomness to belief propagation decoding and uses syndrome voting to achieve far higher accuracy on topological quantum codes while reducing reliance on expensive global decoders.
A two-level decoder scheduling framework reduces classical processing requirements for quantum error correction by 10-40% on fault-tolerant benchmarks by managing bursty workloads as shared resources.
The paper introduces Recursive QLSTM via metacore recursion, numerically tests variants on sequence lengths, and offers theoretical arguments for better temporal propagation.
Review of CMOS compatibility advantages and challenges for semiconductor spin qubits aimed at enabling large-scale fault-tolerant quantum computing.
citing papers explorer
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Enhancing Instruction Prefetching via Cache and TLB Management
IP-CaT jointly optimizes TLB and cache management for L1I prefetching via a translation prefetch buffer and trimodal replacement policy, yielding 8.7% geomean speedup over EPI across 105 server workloads.
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MIPSBLEED: Uncovering Microarchitectural Timing Leaks in Pervasive Embedded Processors
MIPSBLEED uncovers timing leaks in L1 data cache, L1 instruction cache, and execution engine of SMT-enabled MIPS processors and demonstrates a single-trace key recovery attack on elliptic curve cryptography.
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DAE4HLS: Exposing Memory-Level Parallelism for High-Level Synthesis using Explicit Decoupling
DAE4HLS enables explicit decoupling of access and execute in HLS to unlock memory-level parallelism, delivering 10-79x speedups for complex workloads on commercial and dynamic HLS tools.
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C-Phase-Aware Compilation for Efficient Fault-Tolerant Quantum Execution
A microarchitecture-aware compiler for lattice surgery that exploits C-Phase commutativity to enable concurrent multi-target operations and dynamic event-driven scheduling, cutting execution time by up to 59.7 times versus standard baselines.
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Lottery BP: Unlocking Quantum Error Decoding at Scale
Lottery BP adds randomness to belief propagation decoding and uses syndrome voting to achieve far higher accuracy on topological quantum codes while reducing reliance on expensive global decoders.
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Managing Classical Processing Requirements for Quantum Error Correction
A two-level decoder scheduling framework reduces classical processing requirements for quantum error correction by 10-40% on fault-tolerant benchmarks by managing bursty workloads as shared resources.
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Recursive QLSTM with Dynamic Variational Quantum Circuit Adaptation
The paper introduces Recursive QLSTM via metacore recursion, numerically tests variants on sequence lengths, and offers theoretical arguments for better temporal propagation.
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CMOS compatibility of semiconductor spin qubits
Review of CMOS compatibility advantages and challenges for semiconductor spin qubits aimed at enabling large-scale fault-tolerant quantum computing.