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MicroScopiQ: Accelerating Foundational Models through Outlier-Aware Microscaling Quantization

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arxiv 2411.05282 v4 pith:Q6GBTZX3 submitted 2024-11-08 cs.AR cs.AIcs.LG

classification cs.ARcs.AIcs.LG
keywords microscopiqoutliersquantizationaccuracyefficiencyhardwareoutlier-awareprecision
verification ladder T0 review T1 audit T2 compute T3 formal
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Quantization of foundational models (FMs) is significantly more challenging than traditional DNNs due to the emergence of large magnitude values called outliers. Existing outlier-aware algorithm-architecture co-design techniques either use mixed-precision, retaining outliers at high precision but compromise hardware efficiency, or quantize inliers and outliers at the same precision, improving hardware efficiency at the cost of accuracy. To address this mutual exclusivity, we propose MicroScopiQ, a novel co-design technique that leverages pruning to complement outlier-aware quantization. MicroScopiQ retains outliers at higher precision while pruning a certain fraction of least important weights to distribute the additional outlier bits; ensuring high accuracy, aligned memory and hardware efficiency. We design a high-throughput, low overhead accelerator architecture composed of multi-precision INT processing elements and a network-on-chip called ReCoN that efficiently abstracts the complexity of supporting high-precision outliers. Additionally, unlike prior techniques, MicroScopiQ does not assume any locality of outlier weights, enabling applicability to a broad range of FMs. Extensive experiments across diverse quantization settings demonstrate that MicroScopiQ achieves state-of-the-art quantization accuracy, while delivering up to 3x faster inference and 2x lower energy consumption compared to existing alternatives. Code is available at: https://github.com/georgia-tech-synergy-lab/MicroScopiQ-LLM-Quantization

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Cited by 2 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. DSTAR: Accelerating Diffusion Transformers via Spatial and Temporal Redundancy Reduction

    cs.AR 2026-07 conditional novelty 6.0 of 10

    DSTAR reports 7.33x latency speedup and 41.89x energy savings over an A100 GPU on seven diffusion transformers by quantizing differential activations to as few as 2 bits and reusing block-wise sparse attention scores.

  2. AIRCHITECT v2: Learning the Hardware Accelerator Design Space through Unified Representations

    cs.LG 2025-01 conditional novelty 5.0 of 10

    Contrastive learning and a unified ordinal output let a transformer predict optimal accelerator hardware configurations for DNN workloads at constant time, with 91% accuracy on a MAESTRO-based dataset.

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