MATTER: Multi-stage Adaptive Thermal Trojan for Efficiency & Resilience degradation

Abdel-Hameed Badawy; Ahmad Patooghy; Mahdi Fazeli; Mehdi Elahi; Mohamed R. Elshamy

REVIEW 5 major objections 6 minor 3 cited by

MATTER: Multi-stage Adaptive Thermal Trojan for Efficiency & Resilience degradation

T0 review · 5 major / 6 minor · reviewed 2026-08-12 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read A two-stage thermal trojan can cut DTM throttling by up to 73% by making the chip believe it is cooler than it is.

desk verdict A plausible but under-supported attack idea: the claimed new interface isn't shown to be distinct from sensor spoofing, and the numbers need cleaning. read the letter →

arxiv 2412.00226 v1 pith:ZL3EN6RW submitted 2024-11-29 cs.CR cs.AR

Mehdi Elahi , Mohamed R. Elshamy , Abdel-Hameed Badawy , Mahdi Fazeli , Ahmad Patooghy This is my paper · ORCID

classification cs.CRcs.AR

keywords ThermalTrojanDynamicManagement(DTM)DVFSSystem-on-Chip(SoC)securityrunawayhardwaretemperaturesensorinterfaceside-channelthresholdextraction

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper argues that a new class of thermal attack, MATTER, can defeat Dynamic Thermal Management (DTM) without touching the chip's temperature sensors. It works by altering the interface between the peak-temperature identifier and the DVFS controller, so the DTM system believes the chip is cooler than it is. In simulations across compute-, memory-, and mixed-intensity workloads, the attack reduces DTM's throttling effectiveness by up to 73%, raises power consumption, and shifts the power-temperature equilibrium toward thermal runaway. The reason to care is that if this is right, sensor-integrity defenses and average-temperature checks are not enough to protect mobile SoCs from thermal tampering.

What carries the argument

The load-bearing object is the DTM sensed-temperature interface, specifically the path from the peak identifier (which picks the hottest core temperature) to the DVFS control module. MATTER applies a two-stage adaptive offset there: Stage 1 raises the reported temperature by 0.5–1°C to look like natural drift and bank “temperature credits”; Stage 2 lowers the reported temperature by 1.5–2°C and clamps it just below the critical threshold, following the paper's Equation (1). A separate trigger, “thread biasing,” heats one core through the system's thread-manager interface and watches frequency drops and recoveries to learn $T_{\text{critical}}$ and $T_{\text{recovery}}$, the parameters the offset must respect.

What would settle it

An independent test would log raw sensor outputs side by side with the values the DTM actually acts on. If MATTER works, sustained intervals will show real peak temperatures above the critical threshold while the DVFS-reported frequency stays at maximum and the sensed peak stays below threshold. If instead raw and sensed temperatures always agree, or DVFS still throttles when real temperature crosses the threshold, the central claim fails.

Watch

Extended reading notes

Core claim

MATTER's central claim is that the trust boundary of a thermal management system is not the sensor but the sensed-temperature interface. The attacker modifies the peak identifier so that instead of forwarding the maximum real temperature, it forwards an attacked temperature: in Stage 1 it adds 0.5–1°C to build “temperature credits” that keep the average near baseline; in Stage 2 it subtracts 1.5–2°C, clamped to stay just below the critical threshold $T_{\text{critical}}$, so the real temperature crosses the threshold while DVFS keeps the frequency high. The paper reports that throttling events (impactful restricted epochs, IREs) drop by about 73%, power rises, full-load core utilization increases by roughly 38%, and the system's power-temperature fixed point becomes unstable. The attack is claimed to be stealthy under average-temperature comparison because the deviation between trojan-free and trojan-infected chips stays within ±1.2% across configurations from 4 to 48 cores.

Load-bearing premise

The attack works only if the attacker can modify the internal peak-identifier interface while having only ordinary system access, and the paper does not show how that modification is made.

Editorial extensions

If this is right

Under MATTER, the number and duration of DVFS throttling events fall, reducing DTM's measured performance by about 73% on average across the tested workloads.
Power consumption rises: about 18.6% of execution time consumes 17 W or more above baseline, and roughly a fifth of the time sits 12–14 W above baseline.
Core utilization shifts, with time spent in full-load states increasing by about 38%, keeping cores hot for longer stretches.
Power-temperature fixed-point analysis moves from a single stable equilibrium to a regime where a perturbation can push the system into thermal runaway.
Average-temperature checks do not expose the attack: deviations across 4- to 48-core configurations stay within roughly ±1.2%.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

Editorial inference: because MATTER leaves raw sensor readings intact, defenses that check sensor plausibility alone will miss it; a stronger defense would cross-check DVFS decisions against an independent thermal estimate or a second sensing path.
Editorial inference: the same interface, driven in reverse, could force unnecessary throttling and act as a denial-of-service or aging-acceleration vector, not just an efficiency drain.
Editorial inference: randomizing or hiding DTM thresholds, or adding hysteresis noise to DVFS responses, would blunt thread biasing's ability to learn $T_{\text{critical}}$ and $T_{\text{recovery}}$, since the attack's precision depends on those values.

Share X Bluesky LinkedIn Reddit HN

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

The paper's one real idea is to attack the DTM at the peak-identifier-to-DVFS handoff instead of at the thermal sensor itself. That's a legitimate and slightly new angle, and the authors deserve credit for aiming at a specific internal interface rather than rehashing sensor spoofing. They also did actual work: CoMeT simulations with Sniper/McPAT/HotSpot, multiple benchmark suites, a defined IRE metric, and a practical-sounding trigger ("thread biasing") to learn the DTM thresholds. The reported effects—fewer throttling events, more time at full frequency, higher power, and a drift toward thermal instability—are consistent with what an interface-level Trojan should do.

But the central claim doesn't hold up as written. Section III-A grants the attacker access to "system interfaces" (software), while Section III-B requires "subtly manipulating the peak identifier architecture" (hardware). The conclusion tries to have it both ways by saying MATTER could be a hardware or software Trojan, but never explains how a kernel-level attacker reaches an internal hardware signal path. The simulation's Eq. (1) just subtracts a random offset from the current temperature and clamps below a threshold—that is functionally identical to corrupting the sensor readout. No patch or CoMeT configuration is shown to prove the peak identifier module itself was altered. So the novelty over prior sensor attacks is asserted, not demonstrated. The stress-test note is on the mark.

There are also concrete reporting problems. Table I shows a Stage-1 offset of +2.5°C at t=20, but the text says Stage-1 raises temperature by 0.5–1.0°C. The abstract says "as much as 73%" while Section IV-A says "on average" 73%. "DTM performance" is never formally defined; IRE reduction is a reasonable proxy, but calling it "73% degradation in DTM's optimal performance" is overreach. No error bars, and no code or data release.

None of this kills the idea. If the authors respecify the threat model—e.g., a hardware Trojan that overwrites the peak identifier's output register—and fix the reporting, the paper could be solid. As it stands, the work is a suggestive simulation study whose headline novelty isn't backed by the evidence. Worth a serious referee, but it needs major revision before I'd trust the numbers.

Who's it for: architecture and hardware-security researchers looking at thermal side-channels and DTM robustness. I'd bring it to a reading group as a case study in how threat-model sloppiness undermines an otherwise reasonable attack idea.

Recommendation: send to peer review, but push for a precise threat model, internal-consistency fixes, and release of the simulation setup.

Referee Report

5 major / 6 minor

Summary. The paper proposes MATTER, a two-stage thermal Trojan for mobile SoCs that manipulates the temperature information used by Dynamic Thermal Management (DTM). The claimed novelty is that the attack targets the interface between the peak identifier and the DVFS control module, rather than the thermal sensors themselves. The attack is evaluated with the CoMeT simulation toolchain using SPLASH-2, PARSEC, and SPEC CPU2006 benchmarks. The reported results include an approximate 73% reduction in DTM-triggered throttling events (IREs), increased power consumption, higher core utilization, reduced thermal stability, and low average temperature deviation, which the paper interprets as stealthiness.

Significance. If the claims are substantiated, the paper would identify a new attack surface in the DTM thermal sensing path and motivate stronger protections beyond sensor-level countermeasures. The use of a standard open-source simulation toolchain and multiple benchmark suites is a strength, as is the explicit attempt to quantify the impact on throttling events. However, the significance is currently limited by an internally inconsistent threat model and by the fact that the implemented simulation appears functionally equivalent to conventional sensor spoofing. The paper does not provide machine-checked proofs or reproducible code, but the evaluation methodology is, in principle, reproducible with the cited tools.

major comments (5)

[Section III-A and III-B] The threat model states that "the attacker gains access to local resources, i.e., system interfaces" (Section III-A), but Section III-B then requires "subtly manipulating the peak identifier architecture." A software-level attacker with only system-interface access cannot modify an internal hardware peak-identifier module, while a hardware Trojan inserted at that interface would not require the described software access. The paper never explains the mechanism that bridges this gap, and the conclusion's suggestion that the Trojan can be either hardware or software does not resolve it, because neither level is shown to reach the peak identifier.
[Section III-B, Eq. (1)] The attack equation (1) directly subtracts a random offset from "Current Temp" and clamps the result below "Critical - N([0.1, 0.3])". This is functionally identical to falsifying the sensed temperature value before it is used by the DTM. Since no patch or configuration is given showing that CoMeT's peak-identifier module was altered rather than the temperature trace, the central claim of attacking the peak-identifier-to-DVFS interface rather than sensors is unsupported. In fact, the abstract's phrase "manipulating temperature sensor interfaces" is consistent with the implemented simulation.
[Table I] Table I contradicts the stated attack parameters. In Stage 1, at time 20 the attacked temperature is 80.4°C versus real 77.9°C, an offset of +2.5°C, outside the claimed 0.5–1.0°C range. In Stage 2, the offsets at times 30, 40, and 50 are -1.1°C, -2.1°C, and -3.0°C, whereas Eq. (1) specifies a normal distribution with 1.5–2°C reduction. These discrepancies undermine the quantitative calibration of the attack and should be corrected or explained.
[Abstract and Section IV-A] The abstract reports degradation "as much as 73%" while Section IV-A states "on average ... approximate 73% degradation"; these are different claims, and the reader cannot tell which is supported by Figure 3. Moreover, "DTM performance" is never explicitly defined; the paper substitutes the reduction in Impactful Restricted Epochs (IREs) for DTM performance degradation, but does not show how IRE reduction maps to the claimed efficiency and resilience degradation (e.g., instructions per second, energy, or time-to-thermal-runaway).
[Section IV-D, Table II] The stealthiness evaluation is circular: the small average temperature deviations in Table II are a direct consequence of the small offsets and the clamping to Critical - N([0.1,0.3]) in Eq. (1). The paper therefore does not demonstrate resilience to detection; it only restates the attack's parameter choices. A meaningful stealthiness evaluation should run actual countermeasures such as BIC [16] or Kalman-filter-based detection and report detection rates.

minor comments (6)

[Section III] In the introductory paragraph of Section III, "MATEER" appears instead of "MATTER".
[Figure 2] The labels "Tier. 1" and "Tier. 2" in Figure 2 are not defined in the text; presumably they correspond to the trigger and critical thresholds, but this should be stated explicitly.
[Section IV-A] The subsections "Experimental results.1" and "Experimental results.2" use an unusual numbering style; please renumber them as ordinary paragraphs or subsubsections.
[Figures 3–6] Figures 3 through 6 have no error bars and no indication of the number of simulation runs; the authors should state whether these are single-run results and, if so, add variability measures or at least acknowledge the limitation.
[Reference [25]] The citation for CoMeT [25] lacks a venue or version; please provide a complete reference with a technical report number or repository URL.
[Table II] In Table II, the third row's deviation is listed as "+1.2" without a percent sign, and it is the only positive deviation among the four configurations; please clarify the units and discuss this inconsistency.

Circularity Check

2 steps flagged · score 8.0 of 10

MATTER's headline 73% DTM degradation and average-temperature stealth are written into Eq. (1)'s clamp below the critical threshold, so the evaluation results restate the attack definition.

self definitional [Section III-B, Eq. (1); Section IV-A, Experimental results.1]
"Attacked = Current Temp − N([1.5, 2]); Attacked Temp[i] = min(Attacked, Critical − N([0.1, 0.3])) ... This stage strategically maintains the DTM’s sensed temperature just below the critical threshold (e.g., 80°C ...), preventing the DVFS from engaging its protective measures, i.e., core throttling. ... MATTER significantly disrupts DTM in mobile SoCs. On average, these attacks reduce DTM’s ability to manage and balance thermal output effectively, resulting in an approximate 73% degradation in DTM’s optimal performance."

Eq. (1) does not simulate an attack on the peak-identifier/DVFS interface; it directly redefines the sensed temperature, capping it at Critical − N([0.1, 0.3]). Since an IRE is defined as a DVFS reaction to crossing a thermal threshold, the clamp guarantees that critical-threshold reactions cannot occur while the attack is active. The 73% IRE reduction is therefore a mathematical shadow of the clamp, not an independently discovered consequence of MATTER. The attack's defining equations contain the headline result, which is the signature of a self-definitional claim.
self definitional [Section III-B, Eq. (1); Section IV-D, Table II]
"The DTM’s sensed temperature fluctuates within a narrow range, typically between -1.5°C and -2°C, following a normal distribution and simulating natural sensor variations ... Findings presented in Table II demonstrate the resilience of MATTER against detection methods based on average temperature analysis."

The offset ranges in Eq. (1) are chosen to be small (1.5–2°C below current temperature, with a 0.1–0.3°C margin below critical) explicitly 'simulating natural sensor variations.' Average temperature over an execution is then close to the un-attacked average by construction. Reporting Table II's small deviations as 'resilience against detection methods based on average temperature analysis' presents the design parameter as an empirical result. No independent detector, decision threshold, or statistical test is run; the claimed stealthiness reduces to the chosen offset magnitude.

full rationale

The circularity is localized to the quantitative claims that MATTER degrades DTM performance by up to 73% and is stealthy against average-temperature detection. Equation (1) defines the attacked temperature as min(Current Temp − N([1.5,2]), Critical − N([0.1,0.3])). This forces the sensed temperature to sit below the critical threshold whenever the clamp applies, so the absence of critical-threshold DVFS throttling (and hence the large reduction in IREs reported in Section IV-A) is a direct consequence of the attack definition rather than an independent experimental discovery. Likewise, the small average temperature deviations in Table II are produced by the design choice of small offset ranges; no detector was run and no detection threshold was specified, so the stealthiness 'finding' restates the chosen offset magnitude. The paper's claimed novelty—attacking the peak-identifier/DVFS interface rather than the sensor—is not itself circular, but it is also not established: the threat model grants only 'access to local resources, i.e., system interfaces' while the attack requires 'subtly manipulating the peak identifier architecture,' and Eq. (1) is implemented as a direct alteration of the sensed temperature value. That is a threat-model/correctness gap, not a circularity. The self-citations in the paper are background references or the BIC countermeasure being attacked; none is load-bearing in a circular way. The performance simulator (CoMeT/Sniper/HotSpot) is external, so the simulation infrastructure is independent; however, the headline performance and stealth conclusions are forced by the attack's defining equations.

Assumptions & free parameters 3 free parameters · 4 assumptions · 0 invented entities

The only invented concepts are the attack name and the metaphorical 'temperature credits' ledger, which is not a physical entity. The load-bearing free parameters are the temperature offsets, which are hand-picked to achieve the reported stealthiness.

free parameters (3)

Stage-1 temperature offset = +0.5 to +1.0 °C
Chosen to look like natural drift while creating thermal credits; not derived from a physical model.
Stage-2 temperature reduction = N([1.5, 2]) °C
Chosen to keep sensed temperature just below the critical threshold; Table I shows observed reductions of 1.1-1.4°C.
Critical threshold safety margin = N([0.1, 0.3]) °C
Added in Eq. (1) to avoid crossing the critical threshold; arbitrary choice.

assumptions (4)

domain assumption CoMeT simulator with McPAT, CACTI, and HotSpot accurately models SoC thermal and DVFS behavior.
All results depend on this simulation chain; no real-hardware validation is provided.
domain assumption DTM uses the peak temperature across all components to trigger DVFS.
The attack targets the peak identifier; if DTM used per-core sensors or voting, the attack would differ.
ad hoc to paper The attacker can modify the peak-identifier-to-DVFS interface without detection.
Threat model in Section III-A; no implementation details are given for this internal hardware modification.
ad hoc to paper The attack offsets follow a normal distribution with arbitrary parameters.
Eq. (1) uses N([1.5, 2]) and N([0.1, 0.3]) without justification or sensitivity analysis.

how reviews work

0 comments

Cite this review

Pith. "Pith review of MATTER: Multi-stage Adaptive Thermal Trojan for Efficiency & Resilience degradation." pith.science (2026). https://pith.science/paper/ZL3EN6RW

@misc{pith2026241200226,
  author       = {Pith},
  title        = {Pith review of: MATTER: Multi-stage Adaptive Thermal Trojan for Efficiency & Resilience degradation},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/ZL3EN6RW}},
  note         = {Machine review of arXiv:2412.00226}
}

read the original abstract

As mobile systems become more advanced, the security of System-on-Chips (SoCs) is increasingly threatened by thermal attacks. This research introduces a new attack method called the Multi-stage Adaptive Thermal Trojan for Efficiency and Resilience Degradation (MATTER). MATTER takes advantage of weaknesses in Dynamic Thermal Management (DTM) systems by manipulating temperature sensor interfaces, which leads to incorrect thermal sensing and disrupts the SoC's ability to manage heat effectively. Our experiments show that this attack can degrade DTM performance by as much as 73%, highlighting serious vulnerabilities in modern mobile devices. By exploiting the trust placed in temperature sensors, MATTER causes DTM systems to make poor decisions i.e., failing to activate cooling when needed. This not only affects how well the system works but also threatens the lifespan of the hardware. This paper provides a thorough analysis of how MATTER works and emphasizes the need for stronger thermal management systems in SoCs.

Figures

Figures reproduced from arXiv: 2412.00226 by the authors.

**Figure 2.** b), preventing the DVFS from engaging its protective [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗

**Figure 3.** Number and duration of IREs with and without MATTER across different benchmarks: PARSEC (with simmedium [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗

Figures from the paper (3 more)

**Figure 4.** Figure 4: Increased Power Consumption Pre- and Post-Application of the MATTER Attack [PITH_FULL_IMAGE:figures/full_fig_p006_4.png]

**Figure 5.** Figure 5: Relative core resource utilization with and without exposure to the MATTER attack [PITH_FULL_IMAGE:figures/full_fig_p006_5.png]

**Figure 6.** Figure 6: Power-Temperature Dynamics of the stable/unstable [PITH_FULL_IMAGE:figures/full_fig_p007_6.png]

Discussion (0). Continue with ORCID to comment.

Forward citations

Cited by 3 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

CPINN-ABPI: Physics-Informed Neural Networks for Accurate Power Estimation in MPSoCs
cs.PF 2025-05 conditional novelty 5.0 of 10

A physics-informed residual neural network trained on per-unit power labels cuts power estimation error by 74 to 85 percent over the unsupervised ABPI baseline on Jetson hardware and a simulated heterogeneous SoC.
iThermTroj: Exploiting Intermittent Thermal Trojans in Multi-Processor System-on-Chips
cs.CR 2025-07 conditional novelty 4.0 of 10

Intermittent thermal trojans that randomly tamper with SoC temperature readings evade the BIC detector, and tiny ML classifiers can detect these manipulations at a claimed 0.8 degree Celsius resolution.
An Experimental Study of Trojan Vulnerabilities in UAV Autonomous Landing
cs.CR 2025-10 reject novelty 3.0 of 10

A VGG16 landing-pad classifier trained with 30% 5x5-chessboard-triggered images drops from 96.4% to 73.3% accuracy on triggered input.

Reference graph

Works this paper leans on

34 extracted references · 15 canonical work pages · cited by 3 Pith papers

[16]

Bic: Blind identification countermeasure for malicious thermal sensor attacks in mobile socs,

M. Abdelrehim, A. Patooghy, A. Malekmohammadi, and A.-H. A. Badawy, “Bic: Blind identification countermeasure for malicious thermal sensor attacks in mobile socs,” in 2022 23rd International Symposium on Quality Electronic Design (ISQED) . IEEE, 2022, pp. 1–6

2022
[1]

Band: coordinated multi-dnn inference on heterogeneous mobile processors,

J. S. Jeong, J. Lee, D. Kim, C. Jeon, C. Jeong, Y . Lee, and B.-G. Chun, “Band: coordinated multi-dnn inference on heterogeneous mobile processors,” in Proceedings of the 20th Annual International Conference on Mobile Systems, Applications and Services , 2022, pp. 235–247

2022
[2]

Addressing benign and malicious crosstalk in modern system-on- chips,

A. Patooghy, M. Elahi, M. F. Torkaman, S. S. Dokhtfaroughi, and R. Ra- jaei, “Addressing benign and malicious crosstalk in modern system-on- chips,” IEEE Access , vol. 11, pp. 142 263–142 275, 2023

2023
[3]

Your hardware is all wired up! attacking network-on-chips via crosstalk channel,

A. Patooghy, M. F. Torkaman, and M. Elahi, “Your hardware is all wired up! attacking network-on-chips via crosstalk channel,” in Proceedings of the 12th International Workshop on Network on Chip Architectures , 2019, pp. 1–6

2019
[4]

An efficient thermal model of chiplet heterogeneous integration system for steady- state temperature prediction,

C. Wang, Q. Xu, C. Nie, H. Cao, J. Liu, and Z. Li, “An efficient thermal model of chiplet heterogeneous integration system for steady- state temperature prediction,” Microelectronics Reliability, vol. 146, p. 115006, 2023

2023
[5]

Thermal management in mobile devices: challenges and solutions,

Y . Hang and H. Kabban, “Thermal management in mobile devices: challenges and solutions,” in 2015 31st Thermal Measurement, Modeling & Management Symposium (SEMI-THERM) , 2015, pp. 46–49

work page 2015
[6]

Machine learning for power, energy, and thermal management on multicore processors: A survey,

S. Pagani, P. D. S. Manoj, A. Jantsch, and J. Henkel, “Machine learning for power, energy, and thermal management on multicore processors: A survey,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 39, no. 1, pp. 101–116, 2020

2020
[7]

Performance assessment and optimization of a thin-film thermoelectric cooler for on- chip transient thermal management,

T. Gong, L. Li, M. Shi, L. Kang, L. Gao, and J. Li, “Performance assessment and optimization of a thin-film thermoelectric cooler for on- chip transient thermal management,” Applied Thermal Engineering , vol. 224, p. 120079, 2023

2023

Show all 34 references

[8]

3dep: A efficient routing algorithm to evenly distribute traffic over 3d network- on-chips,

F. Vahdatpanah, M. Elahi, S. Kashi, E. Taheri, and A. Patooghy, “3dep: A efficient routing algorithm to evenly distribute traffic over 3d network- on-chips,” in 2019 27th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP) , 2019, pp. 237–241

2019
[9]

Compact thermal- diffusivity-based temperature sensors in 40-nm cmos for soc thermal monitoring,

U. S ¨onmez, F. Sebastiano, and K. A. Makinwa, “Compact thermal- diffusivity-based temperature sensors in 40-nm cmos for soc thermal monitoring,” IEEE Journal of Solid-State Circuits , vol. 52, no. 3, pp. 834–843, 2017

2017
[10]

A novel thermal management scheme for 3d-ic chips with multi-cores and high power density,

B. Ding, Z.-H. Zhang, L. Gong, M.-H. Xu, and Z.-Q. Huang, “A novel thermal management scheme for 3d-ic chips with multi-cores and high power density,” Applied thermal engineering , vol. 168, p. 114832, 2020

2020
[11]

Fem-based thermal profile prediction for thermal management of system-on-chips,

A. Oukaira, D. E. Touati, A. Hassan, M. Ali, Y . Savaria, and A. Lakhssassi, “Fem-based thermal profile prediction for thermal management of system-on-chips,” 2022 8th International Conference on Optimization and Applications (ICOA) , pp. 1–4, 2022. [Online]. Available: https:...

2022
[12]

Untrimmed low-power thermal sensor for soc in 22 nm digital fabrication technology,

R. Eitan and A. Cohen, “Untrimmed low-power thermal sensor for soc in 22 nm digital fabrication technology,” Journal of Low Power Electronics and Applications , vol. 4, no. 4, pp. 304–316, 2014. [Online]. Available: https://www.mdpi.com/2079-9268/4/4/304

2014
[13]

Node-wise hardware trojan detection based on graph learning,

K. Hasegawa, K. Yamashita, S. Hidano, K. Fukushima, K. Hashimoto, and N. Togawa, “Node-wise hardware trojan detection based on graph learning,” IEEE Transactions on Computers , 2023

2023
[14]

Accurate on-chip temperature sensing for multicore processors using embedded thermal sensors,

X. Li, Z. Li, W. Zhou, and Z. Duan, “Accurate on-chip temperature sensing for multicore processors using embedded thermal sensors,” IEEE Transactions on V ery Large Scale Integration (VLSI) Systems , vol. 28, no. 11, pp. 2328–2341, 2020

2020
[15]

Auto- matic hardware trojan insertion using machine learning,

J. Cruz, P. Gaikwad, A. Nair, P. Chakraborty, and S. Bhunia, “Auto- matic hardware trojan insertion using machine learning,” arXiv preprint arXiv:2204.08580, 2022

2022 arXiv
[17]

Understanding the sources of power consumption in mobile socs,

M. Said, S. Chetoui, A. Belouchrani, and S. Reda, “Understanding the sources of power consumption in mobile socs,” in 2018 Ninth International Green and Sustainable Computing Conference (IGSC) . IEEE, 2018, pp. 1–7

2018
[18]

Proactive temperature bal- ancing for low cost thermal management in mpsocs,

A. K. Coskun, T. S. Rosing, and K. C. Gross, “Proactive temperature bal- ancing for low cost thermal management in mpsocs,” in2008 IEEE/ACM International Conference on Computer-Aided Design . IEEE, 2008, pp. 250–257

2008
[19]

Accurate direct and indirect on-chip temperature sensing for efficient dynamic thermal management,

S. Sharifi and T. ˇS. Rosing, “Accurate direct and indirect on-chip temperature sensing for efficient dynamic thermal management,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 10, pp. 1586–1599, 2010

2010
[20]

On-chip thermal profiling to detect malicious activity: System-level concepts and design of key building blocks,

M. Yan, H. Wei, and M. Onabajo, “On-chip thermal profiling to detect malicious activity: System-level concepts and design of key building blocks,” IEEE Transactions on V ery Large Scale Integration (VLSI) Systems, vol. 29, no. 3, pp. 530–543, 2021

2021
[21]

Securing iot space via hardware trojan detection,

S. Guo, J. Wang, Z. Chen, Y . Li, and Z. Lu, “Securing iot space via hardware trojan detection,” IEEE Internet of Things Journal , vol. 7, no. 11, pp. 11 115–11 122, 2020

2020
[22]

Circuit enclaves susceptible to hardware trojans insertion at gate-level designs,

S. M. Sebt, A. Patooghy, H. Beitollahi, and M. Kinsy, “Circuit enclaves susceptible to hardware trojans insertion at gate-level designs,” IET Computers & Digital Techniques , vol. 12, no. 6, pp. 251–257, 2018

2018
[23]

Detrust: Defeating hardware trust verification with stealthy implicitly-triggered hardware trojans,

J. Zhang, F. Yuan, and Q. Xu, “Detrust: Defeating hardware trust verification with stealthy implicitly-triggered hardware trojans,” in Pro- ceedings of the 2014 ACM SIGSAC conference on computer and communications security , 2014, pp. 153–166

2014
[24]

Mukhopadhyay and R

D. Mukhopadhyay and R. S. Chakraborty, Hardware security: design, threats, and safeguards . CRC Press, 2014

2014
[25]

Comet: An integrated interval thermal simulation toolchain for 2d, 2.5 d, and 3d processor-memory systems,

R. Kedia, “Comet: An integrated interval thermal simulation toolchain for 2d, 2.5 d, and 3d processor-memory systems,” 2022

2022
[26]

Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation,

T. E. Carlson, W. Heirman, and L. Eeckhout, “Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation,” in Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis , 2011, pp. 1–12

2011
[27]

Mcpat: An integrated power, area, and timing modeling framework for multicore and manycore architectures,

S. Li, J. H. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi, “Mcpat: An integrated power, area, and timing modeling framework for multicore and manycore architectures,” in Proceedings of the 42nd annual ieee/acm international symposium on microarchitecture,...

2009
[28]

Cacti 7: New tools for interconnect exploration in innovative off-chip memories,

R. Balasubramonian, A. B. Kahng, N. Muralimanohar, A. Shafiee, and V . Srinivas, “Cacti 7: New tools for interconnect exploration in innovative off-chip memories,” ACM Transactions on Architecture and Code Optimization (TACO) , vol. 14, no. 2, pp. 1–25, 2017

2017
[29]

Hotspot: A compact thermal modeling methodology for early-stage vlsi design,

W. Huang, S. Ghosh, S. Velusamy, K. Sankaranarayanan, K. Skadron, and M. R. Stan, “Hotspot: A compact thermal modeling methodology for early-stage vlsi design,” IEEE Transactions on very large scale integration (VLSI) systems , vol. 14, no. 5, pp. 501–513, 2006

2006
[30]

Intel® Xeon® Processor X5550 product specification,

“Intel® Xeon® Processor X5550 product specification,” https://ark.intel.com/content/www/us/en/ark/products/37106/intel- xeon-processor-x5550-8m-cache-2-66-ghz-6-40-gt-s-intel-qpi.html, accessed: 2024-05-20

2024
[31]

The splash- 2 programs: Characterization and methodological considerations,

S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta, “The splash- 2 programs: Characterization and methodological considerations,” ACM SIGARCH computer architecture news , vol. 23, no. 2, pp. 24–36, 1995

1995
[32]

The parsec benchmark suite: Characterization and architectural implications,

C. Bienia, S. Kumar, J. P. Singh, and K. Li, “The parsec benchmark suite: Characterization and architectural implications,” in Proceedings of the 17th international conference on Parallel architectures and compilation techniques, 2008, pp. 72–81

2008
[33]

Potential thermal security risks,

P. Dadvar and K. Skadron, “Potential thermal security risks,” in Semi- conductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005. IEEE, 2005, pp. 229–234

2005
[34]

Power-temperature stability and safety analysis for multiprocessor systems,

G. Bhat, S. Gumussoy, and U. Y . Ogras, “Power-temperature stability and safety analysis for multiprocessor systems,” ACM Transactions on Embedded Computing Systems (TECS) , vol. 16, no. 5s, pp. 1–19, 2017

2017

Pith tools

Reviewed August 12, 2026 · model on record in the stance chip above.

[1] [16]

Bic: Blind identification countermeasure for malicious thermal sensor attacks in mobile socs,

M. Abdelrehim, A. Patooghy, A. Malekmohammadi, and A.-H. A. Badawy, “Bic: Blind identification countermeasure for malicious thermal sensor attacks in mobile socs,” in 2022 23rd International Symposium on Quality Electronic Design (ISQED) . IEEE, 2022, pp. 1–6

2022

[2] [1]

Band: coordinated multi-dnn inference on heterogeneous mobile processors,

J. S. Jeong, J. Lee, D. Kim, C. Jeon, C. Jeong, Y . Lee, and B.-G. Chun, “Band: coordinated multi-dnn inference on heterogeneous mobile processors,” in Proceedings of the 20th Annual International Conference on Mobile Systems, Applications and Services , 2022, pp. 235–247

2022

[3] [2]

Addressing benign and malicious crosstalk in modern system-on- chips,

A. Patooghy, M. Elahi, M. F. Torkaman, S. S. Dokhtfaroughi, and R. Ra- jaei, “Addressing benign and malicious crosstalk in modern system-on- chips,” IEEE Access , vol. 11, pp. 142 263–142 275, 2023

2023

[4] [3]

Your hardware is all wired up! attacking network-on-chips via crosstalk channel,

A. Patooghy, M. F. Torkaman, and M. Elahi, “Your hardware is all wired up! attacking network-on-chips via crosstalk channel,” in Proceedings of the 12th International Workshop on Network on Chip Architectures , 2019, pp. 1–6

2019

[5] [4]

An efficient thermal model of chiplet heterogeneous integration system for steady- state temperature prediction,

C. Wang, Q. Xu, C. Nie, H. Cao, J. Liu, and Z. Li, “An efficient thermal model of chiplet heterogeneous integration system for steady- state temperature prediction,” Microelectronics Reliability, vol. 146, p. 115006, 2023

2023

[6] [5]

Thermal management in mobile devices: challenges and solutions,

Y . Hang and H. Kabban, “Thermal management in mobile devices: challenges and solutions,” in 2015 31st Thermal Measurement, Modeling & Management Symposium (SEMI-THERM) , 2015, pp. 46–49

work page 2015

[7] [6]

Machine learning for power, energy, and thermal management on multicore processors: A survey,

S. Pagani, P. D. S. Manoj, A. Jantsch, and J. Henkel, “Machine learning for power, energy, and thermal management on multicore processors: A survey,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 39, no. 1, pp. 101–116, 2020

2020

[8] [7]

Performance assessment and optimization of a thin-film thermoelectric cooler for on- chip transient thermal management,

T. Gong, L. Li, M. Shi, L. Kang, L. Gao, and J. Li, “Performance assessment and optimization of a thin-film thermoelectric cooler for on- chip transient thermal management,” Applied Thermal Engineering , vol. 224, p. 120079, 2023

2023