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REVIEW 4 major objections 5 minor 41 references

IMPLY-based Approximate Full Adders for Efficient Arithmetic Operations in Image Processing and Machine Learning

T0 review · 4 major / 5 minor · reviewed 2026-08-11 · deepseek-v4-flash

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Pith's one-line read This paper claims that two serial IMPLY-based approximate full adders, SAPPI-1 and SAPPI-2, cut ripple-carry adder steps by 39%–41% and energy by 39%–42% while keeping image quality and MNIST accuracy intact.

desk verdict Two new serial IMPLY approximate adders with real step-count wins, but the energy-savings claim rests on an isolated-cell model and the boolean equations have errors that need fixing. read the letter →

arxiv 2412.15888 v1 pith:5KQUC76Q submitted 2024-12-20 cs.ET cs.LG

Melanie Qiu , Caoyueshan Fan , Gulafshan , Salar Shakibhamedan , Fabian Seiler , Nima TaheriNejad This is my paper · ORCID
classification cs.ETcs.LG
keywords IMPLYlogicmemristorapproximatecomputingin-memoryfulladderripplecarryimageprocessingMNIST
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper tries to establish that approximate computing and memristor-based in-memory computing can be combined in a single adder design without sacrificing the quality of real workloads. It proposes two serial IMPLY-based approximate full adders, SAPPI-1 and SAPPI-2, which, when placed in the low bits of a ripple-carry adder, use 39%–41% fewer steps and 39%–42% less energy than the exact serial IMPLY adder. The point of caring is that addition is the workhorse of image processing and neural-network inference, so a cheap approximate adder could reduce the energy and latency of those applications while living inside memory, avoiding the Von Neumann bottleneck. The paper supports this with circuit-level LT-SPICE simulations, error metrics, image-processing quality metrics, and MNIST case studies.

What carries the argument

In the serial IMPLY topology, one IMPLY or FALSE operation runs per cycle and the second operand is overwritten. SAPPI turns this overwrite into the computation: reset the work memristor $M$ to 0 (FALSE), then $A \to M$ gives $\overline{A}$, then $B \to M$ gives $\overline{AB}$ (the Sum for SAPPI-1), then $M \to C$ gives $AB + C$ (the carry-out for both). SAPPI-2 adds a fifth step, $C' \to A$, which stores the Sum in the A-memristor and changes the error pattern so that the '001' mistake is partially mitigated. The key object is the reusable work memristor plus the carry-in memristor that is overwritten once, giving a defined error rate of 1/8 for Cout and 4/8 for Sum.

What would settle it

Build an 8-bit ripple-carry adder with four SAPPI-1 (or SAPPI-2) low bits and four exact bits on a real integrated memristive crossbar, run all 65,536 input pairs, and compare the total cycle count and energy to the exact 22n-step adder; if the measured savings is below 39% in either steps or energy, because of extra carry-propagation cycles, signal restoration, or non-additive per-bit energy, the paper's central quantitative claim is refuted.

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Extended reading notes

Core claim

The central discovery is that the destructive overwrite behavior of IMPLY logic can itself be used as a design resource rather than a liability. By sequentially implicating the two input memristors into a reset work memristor, the algorithms form the sum as a NAND of the inputs in four steps (SAPPI-1) or five steps (SAPPI-2), and form the carry-out by implicating that intermediate result into the carry-in memristor. The deliberate approximation is concentrated: the carry-out is wrong only for the input pattern '001', and the sum is wrong in four of eight input combinations. SAPPI-1 preserves both input states after the operation, which the authors describe as the first IMPLY adder to do so, at the cost of extra work memristors; SAPPI-2 writes the sum into the A-memristor, which matches the exact serial algorithm's interface. The paper claims these designs beat the exact adder by 39%–42% in energy and 39%–41% in steps, beat the state-of-the-art approximate IMPLY adders by 9%–13% in energy and 7%–10% in steps, keep PSNR above 30 dB in three image-processing tasks with up to half of the RCA approximated, and preserve MNIST accuracy in a CNN with up to four approximated adders.

Load-bearing premise

The savings figures assume that the energy and step counts of a whole ripple-carry adder are just the sums of the per-bit values, with no extra work when a carry passes between slices, and that the behavior measured on discrete memristors carries over to integrated devices; the authors note integrated devices should be faster and use less power, but the 39%–42% numbers depend on that transfer.

Editorial extensions

If this is right

  • In an n-bit ripple-carry adder with k approximated low bits, SAPPI-1 gives $4k + 22(n-k)$ steps and SAPPI-2 gives $5k + 22(n-k)$ steps, versus $22n$ for the exact adder, yielding the claimed 39%–41% step savings.
  • For image addition and grayscale conversion, both algorithms keep PSNR above 30 dB with up to 4/8 approximated adders; for Gaussian smoothing, the threshold is reached with up to 8/20 approximated adders.
  • In MNIST classification with a partially approximated 20-bit RCA inside a shift-and-add multiplier, a fully connected network keeps accuracy up to six approximated adders and a LeNet-5-style CNN up to four approximated adders, with SAPPI-1 saving up to 296 mJ (21%) and 1.33 billion steps (20%) per CNN inference.
  • Because SAPPI-1 preserves both input memristor states, the same input data can be reused for later computations without reloading, which prior IMPLY adder designs cannot do.
  • The approximation degree is reconfigurable per run because IMPLY adders are algorithm-defined, so the same hardware can trade accuracy for efficiency depending on the application's error tolerance.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The paper does not explore composing SAPPI with error-correction or prediction circuits: since the only carry error is the '001' pattern, a cheap decoder could detect and fix most of the damage, potentially extending the acceptable approximation degree beyond 4/8.
  • If the additive energy model holds on integrated devices, the same percentage savings should carry over to wider adders and to multipliers, so a natural next check is measuring a full 32-bit RCA or a multiplier in an integrated memory array rather than extrapolating from per-bit simulation.
  • Because SAPPI-1 preserves both operands, it may enable iterative in-memory algorithms such as accumulation or averaging that reuse the same inputs many times; the paper only demonstrates single-pass addition and multiplication, leaving this potential implicit.
  • The trade-off between SAPPI-1's lower energy per bit and SAPPI-2's better error metrics at high approximation degrees suggests a runtime-selectable knob within the same adder family, which could be tuned per bit based on application sensitivity.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. This manuscript proposes two approximate full adders, SAPPI-1 and SAPPI-2, for serial memristive IMPLY logic. SAPPI-1 uses 4 steps per bit and stores the Sum in a work memristor while preserving the A and B operands; SAPPI-2 uses 5 steps per bit and stores the Sum in the A memristor. The authors verify all eight input combinations with LT-SPICE using the VTEAM model under up to +-30% resistance variation, report per-cell energy and step counts, and combine them in linear RCA formulas to claim 39%-41% step and 39%-42% energy reductions against an exact serial adder. They then evaluate partially approximated RCAs in three image-processing tasks using PSNR/MSSIM and in FC-NN/CNN classifiers on MNIST, reporting application-level energy and step savings while maintaining accuracy.

Significance. If the step and energy claims survive scrutiny in a realistic crossbar setting, the contribution is useful: a very short 4-step per-bit serial IMPLY adder with an acceptable error profile for image processing, plus one of the first demonstrations of approximate IMPLY adders in CNN inference. The algorithmic step count reduction is well defined and independent of device models, and the SPICE verification with resistance variation is a concrete strength. The paper is also honest in reporting that its re-simulations of baseline circuits do not match the published values. The main obstacles are the incorrect Boolean equations for Sum and the unvalidated additive energy model, both of which must be fixed before the headline quantitative claims can be accepted.

major comments (4)
  1. [Eq. (1) and Eq. (3), Section III-B/III-C] Equation (1) states Sum = B -> A = AB. In Boolean algebra B -> A is not AB but not-B or A, and the step sequence in Table II actually implements M = not(A) or not(B) = NAND(A,B), which is what the truth table shows. Equation (3) is likewise inconsistent with Table III: step 5 writes C' -> A, which yields Sum = A or not(C), not AB + C + A. The authors should correct these Boolean expressions and the notation B -> A, since the step sequences and truth tables are otherwise self-consistent.
  2. [Section V-A, Eqs. (5)-(6)] The energy claims rest on per-bit energies measured from isolated two-memristor cells and then summed linearly over k approximate and n-k exact bits. In a real serial IMPLY crossbar, cells share word-line and bit-line drivers, so every IMPLY or FALSE step also charges shared lines and can create sneak-path currents that are absent in isolated-cell LT-SPICE runs. The footnote in Table VII already reports unexplained discrepancies between the authors' re-simulations and the published values for [23] and [32]. Because the 39%-42% energy reduction is a headline result, the authors should either simulate a multi-bit crossbar or provide a concrete overhead model demonstrating that shared-line effects do not materially change the claimed savings.
  3. [Section III-A and Introduction] The paper states that the proposed approach is the first adder algorithm that maintains all input states after the operation. This is not literally true: SAPPI-1 overwrites the carry input C in step 4, and SAPPI-2 additionally overwrites A in step 5. If the claim refers only to the A and B operands, it should be stated that way; as written, it overstates the property.
  4. [Section VII-B and Table VIII] The application-level energy and step savings for the CNN inference (296 mJ, 1.33 billion steps) and for image processing are computed by extrapolating per-bit adder savings through the shift-and-add multiplier, but the paper does not describe the calculation or account for the cost of loading operands, storing partial products, or moving data between memristors in the serial topology. The authors should provide the derivation for these application-level numbers, or clearly state which overheads are excluded, so that the ML and image-processing savings are reproducible.
minor comments (5)
  1. [Figs. 2 and 3] The time axis label reads 'Time in s', but the simulations use 30 us pulses; the label should be 'Time in us' or the axis should be rescaled.
  2. [Section III-B and Section V-C] The text in Section III-B says an n-bit addition using only SAPPI-1 requires 3n+1 memristors, while Section V-C and Table VII report 2n+k+3 memristors for a mixed RCA; these counts should be reconciled with a clear definition of n and k.
  3. [References] References [20] and [35] appear to be the same paper and should be merged or distinguished.
  4. [Section VI-B] The sentence 'our approach is not able to reach the 30dB threshold of PSNR with 5/8 approximated adders' should specify that this refers to the evaluated image-processing tasks, since the ML experiments still show acceptable accuracy at some approximation degrees.
  5. [Section VII and Fig. 5] The text gives accuracy thresholds but not the exact accuracy values or the formula used to compute energy savings for the FC-NN and CNN experiments; adding a short description of the calculation and a table of the accuracy numbers would improve reproducibility.

Circularity Check

0 steps flagged · score 2.0 of 10

No significant circularity: the step and energy savings are arithmetic consequences of per-full-adder step counts and SPICE energy measurements, not of fitted parameters; minor self-citation in the exact baseline does not make the derivation circular.

full rationale

The paper's central quantitative claims are not circular. SAPPI-1 and SAPPI-2 are defined by the IMPLY step sequences in Tables II and III, giving 4 and 5 steps per full adder. The exact serial adder [19] is an independent, published algorithm with 22 steps per bit; this count is not derived from the proposed adders. The energy savings rest on Eqs. (5)-(6), where the coefficients 0.7980 nJ, 1.0919 nJ and 4.8250 nJ are the mean per-full-adder energies measured in LT-SPICE under the stated VTEAM parameters (Tables IV-V), not parameters fitted to reproduce the 39%-42% claim. Total energy is then a linear sum over k approximated and n-k exact bits; the claimed savings are the arithmetic difference of these measured values, so no quantity is defined in terms of the result it is supposed to predict. The application-level savings (Tables VIII and Figure 5) are the same per-adder values scaled by image size or MNIST inference operation counts, which is a scaling calculation, not a new fitted prediction. The main self-citation is the choice of [19] (Rohani and TaheriNejad, same group) as the 'exact algorithm' baseline, and the VTEAM SPICE implementation [33] by the same group; this is a minor baseline choice, not a load-bearing circular step, because [19]'s step count is externally checkable and an independent exact adder [35] is also tabulated. The footnote to Table VII explicitly reports that the authors' re-simulations of [23] and [32] differ from the published values ('we are not sure why'), which is a calibration/reliability limitation in the SoA comparison; it weakens the 'up to 10%/13% over SoA' sub-claim but does not make the derivation circular.

Assumptions & free parameters 3 free parameters · 4 assumptions · 0 invented entities

The central claims rest on simulation-derived energy coefficients, additivity of per-bit costs, and the transferability of a discrete-device SPICE model to integrated memristors. No new physical entities are introduced.

free parameters (3)
  • E_approx_SAPPI1 = 0.7980 nJ per bit
    Mean simulated energy per approximated full-adder bit from LT-SPICE, used in Eq. (5); changes with memristor parameters or integration assumptions.
  • E_approx_SAPPI2 = 1.0919 nJ per bit
    Mean simulated energy per approximated bit for SAPPI-2, used in Eq. (6).
  • E_exact = 4.8250 nJ per bit
    Mean simulated energy per exact serial adder bit from re-simulating [19], used as the baseline for all savings claims.
assumptions (4)
  • domain assumption IMPLY operation follows P to Q = not-P or Q and overwrites the second operand; memristor resistances satisfy Ron << RG << Roff and voltage constraints VCOND < VC < VSET.
    Stated in Section II and used to design all step sequences; taken from prior memristor literature.
  • domain assumption Energy and step counts of an n-bit RCA are additive sums of per-bit energies and steps, as in Eqs. (5)-(8), with no inter-bit or crossbar-level overhead.
    Used to compute the total savings percentages in Sections V through VII.
  • domain assumption LT-SPICE VTEAM model parameters in Tables IV and V, fitted to discrete Knowm devices, are representative enough to extrapolate to integrated memristors.
    All quantitative energy and waveform claims rely on these simulations; the authors note in Section IV-A that integrated devices are expected to perform better.
  • domain assumption All eight input combinations are equally weighted when computing error metrics MED, NMED, and MRED.
    Used for Table VI; actual application input distributions may differ, which would change the reported error values.

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Pith. "Pith review of IMPLY-based Approximate Full Adders for Efficient Arithmetic Operations in Image Processing and Machine Learning." pith.science (2026). https://pith.science/paper/5KQUC76Q

@misc{pith2026241215888,
  author       = {Pith},
  title        = {Pith review of: IMPLY-based Approximate Full Adders for Efficient Arithmetic Operations in Image Processing and Machine Learning},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/5KQUC76Q}},
  note         = {Machine review of arXiv:2412.15888}
}
read the original abstract

To overcome the performance limitations in modern computing, such as the power wall, emerging computing paradigms are gaining increasing importance. Approximate computing offers a promising solution by substantially enhancing energy efficiency and reducing latency, albeit with a trade-off in accuracy. Another emerging method is memristor-based In-Memory Computing (IMC) which has the potential to overcome the Von Neumann bottleneck. In this work, we combine these two approaches and propose two Serial APProximate IMPLY-based full adders (SAPPI). When embedded in a Ripple Carry Adder (RCA), our designs reduce the number of steps by 39%-41% and the energy consumption by 39%-42% compared to the exact algorithm. We evaluated our approach at the circuit level and compared it with State-of-the-Art (SoA) approximations where our adders improved the speed by up to 10% and the energy efficiency by up to 13%. We applied our designs in three common image processing applications where we achieved acceptable image quality with up to half of the RCA approximated. We performed a case study to demonstrate the applicability of our approximations in Machine Learning (ML) underscoring the potential gains in more complex scenarios. The proposed approach demonstrates energy savings of up to 296 mJ (21%) and a reduction of 1.3 billion (20%) computational steps when applied to Convolutional Neural Networks (CNNs) trained on the MNIST dataset while maintaining accuracy.

Figures

Figures reproduced from arXiv: 2412.15888 by the authors.

Figure 1
Figure 1. IMPLY operation: (top) Basic Gate and Truth Table, [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 3
Figure 3. B. Simulation Results For both presented algorithms, we evaluated all eight input combinations with deviations of up to ±30%. All combina￾tions agree with the intended behavior as Sum and Cout match the corresponding truth table. Each step in the algorithms cor￾responds to 30µs in the simulations. We arbitrarily illustrated one exact and one incorrect by-design case for SAPPI-1 in [PITH_FULL_IMAGE:figures/full_fig_… view at source ↗
Figure 2
Figure 2. The Sum output is saved in the M1-memristor at 60µs-90µs which corresponds to the third step. In the fourth step from 90µs-120µs, the Cout is stored in the C-memristor. The waveforms for SAPPI-2 are shown in [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figures from the paper (4 more)
Figure 3
Figure 3. Figure 3: Two example simulations of SAPPI-2, illustrating the [PITH_FULL_IMAGE:figures/full_fig_p004_3.png]
Figure 2
Figure 2. Figure 2: Two example simulations of SAPPI-1, illustrating the [PITH_FULL_IMAGE:figures/full_fig_p004_2.png]
Figure 4
Figure 4. Figure 4: Results of different image processing applications [PITH_FULL_IMAGE:figures/full_fig_p005_4.png]
Figure 5
Figure 5. Figure 5: Results of MNIST using the proposed approximations [PITH_FULL_IMAGE:figures/full_fig_p006_5.png]

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