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REVIEW 5 major objections 5 minor 35 references

Efficient Split Learning LSTM Models for FPGA-based Edge IoT Devices

T0 review · 5 major / 5 minor · reviewed 2026-08-08 · deepseek-v4-flash

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Pith's one-line read By combining knowledge distillation, pruning, and quantization, the authors shrink an LSTM water-quality forecaster 45.90x while keeping its coefficient of determination at 0.96, and show that the FPGA split point determines whether an…

desk verdict Genuine engineering case study with honest hardware numbers, but the deployed model's accuracy is never measured and the split-learning label overshoots the implementation. read the letter →

arxiv 2502.08692 v1 pith:DQWXPC2G submitted 2025-02-12 cs.LG cs.DC

Romina Soledad Molina , Vukan Ninkovic , Dejan Vukobratovic , Maria Liz Crespo , Marco Zennaro This is my paper · ORCID
classification cs.LGcs.DC
keywords splitlearningLSTMFPGAaccelerationknowledgedistillationpruningquantizationtime-seriesforecastingwaterqualitymonitoring
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Split learning, which cuts a neural network so the edge device computes only the first layers and a server finishes the prediction, is usually discussed as a way to save communication and privacy. This paper shows that on a low-power FPGA, the more pressing question is where to make that cut. The authors train a 39,951-parameter LSTM teacher for dissolved-oxygen forecasting, distill it into an 871-parameter student using knowledge distillation, prune to 70 percent sparsity, quantize to 8-bit fixed point, and shrink the model $45.90\times$ with only a one-point drop in $R^2$ (0.97 to 0.96). They then synthesize three FPGA variants that differ in the split point between edge and server. The measured result is a design map: full edge inference is fastest at 2.82 microseconds and 0.887 watts, while a single-LSTM split uses 28 percent of LUTs and 0.829 watts and leaves room for two parallel accelerators, at a higher 3.54 microseconds latency.

What carries the argument

The load-bearing mechanism is a four-stage compression and deployment chain: knowledge distillation with a teacher LSTM and an MSE-based distillation loss, post-pruning to 70 percent sparsity, 8-bit fixed-point quantization, and a high-level synthesis flow that converts the student into LSTM hardware accelerators on the FPGA. The compression chain is what turns a 39,951-parameter teacher into an 871-parameter student whose accuracy nearly matches, and the split-point choice is what turns the freed resources into either lower power and lower latency or multiple parallel accelerators.

What would settle it

Measure the actual FPGA accelerator's outputs on the held-out 30 percent test set and compare MAE, MSE, and R2 against the software student's values of 0.0574, 0.0087, and 0.96; agreement supports the deployment claim, while any substantial discrepancy shows the hardware implementation does not deliver the reported accuracy.

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Extended reading notes

Core claim

On the paper's own terms, the central discovery is that combining knowledge distillation, pruning, and quantization compresses an LSTM water-quality forecaster by a factor of $45.90\times$ in memory footprint, from 156.06 KB and 39,951 parameters to 3.40 KB and 871 parameters, while the coefficient of determination falls only from 0.97 to 0.96. When the student is mapped onto an Artix-7 FPGA, the split point between edge and server becomes the main design lever: full edge inference (LSTM-DO-S) achieves $2.82\,\mu s$ latency at 0.887 W, whereas the single-LSTM split (Split-B) drops power to 0.829 W, uses 28 percent of LUTs, and fits two accelerators on the chip (scalability 2) at $3.54\,\mu s$. The authors take this as evidence that split-point selection, not only compression, determines whether a split-learning deployment favors speed, balance, or resource efficiency.

Load-bearing premise

The deployed FPGA version actually reproduces the software student's accuracy; only the software model is evaluated in the accuracy table, so the hardware's true error is assumed rather than measured.

Editorial extensions

If this is right

  • A $45.90\times$ model-size cut with $R^2$ moving only from 0.97 to 0.96 implies memory-limited edge nodes can host useful forecasting models.
  • Split-B's scalability of 2 means one low-end FPGA can run two LSTM accelerators simultaneously, so a single buoy can serve multiple sensor streams in parallel.
  • The reported table gives deployers a concrete operating-point menu: LSTM-DO-S for lowest latency, Split-A for a balanced profile, and Split-B for lowest power and highest parallelism.
  • Because the two split points produce intermediate representations of size 5 and 150, the cost of moving data between memory and the inference core depends strongly on where the split is placed.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Beyond the paper, the same recipe should extend to the other six water parameters the dataset records, since the system is multivariate-ready; a testable next step is training per-parameter students and measuring multi-accelerator throughput.
  • Beyond the paper, split-point selection can be read as a hardware-batch-size knob: moving layers to the server frees on-chip resources that reappear as extra parallel accelerators, a principle likely to carry over to other recurrent architectures.
  • Beyond the paper, one decisive check is left undone: an end-to-end accuracy measurement of the quantized FPGA implementation against the software student would directly confirm or refute the paper's claim of only slight performance degradation.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

5 major / 5 minor

Summary. This paper reports a practical deployment study of split-learning LSTM models on a low-end Artix-7 FPGA for river-water dissolved-oxygen forecasting. The authors train an LSTM teacher and a smaller knowledge-distilled student, apply 70% pruning and 8-bit quantization, synthesize the compressed student with hls4ml, and evaluate three hardware configurations (full student, Split-A with two on-FPGA LSTM layers, and Split-B with one on-FPGA LSTM layer) in terms of resource utilization, latency, power, and scalability. The headline results are a 45.90x size reduction (156.06 KB to 3.40 KB) with the software student retaining R2 = 0.96 versus 0.97 for the teacher, and a split-point trade-off in which Split-B uses fewer resources and lower power at somewhat higher latency while enabling two parallel accelerators.

Significance. If the claims are substantiated, this is a useful end-to-end demonstration that knowledge distillation, pruning, and quantization can fit an LSTM edge model onto a small FPGA, with concrete hardware trade-offs that are easy to reproduce. The strengths are the real hardware evaluation on a specific FPGA board, the use of hls4ml, the explicit scalability metric, and the hardware evaluation framework. The distinction among LSTM-DO-S, Split-A, and Split-B is a practical and clearly presented trade-off. However, the paper does not verify that the deployed fixed-point accelerator preserves the reported software accuracy, and the reported model size is inconsistent with the stated 8-bit quantization. These gaps must be closed before the central accuracy-efficiency trade-off can be accepted.

major comments (5)
  1. [Section IV-C, Table II; Section V] The deployed hardware model's prediction accuracy is never measured. Table II reports MAE, MSE, and R2 for the Keras teacher and student only; the hls4ml-synthesized fixed-point accelerator is not evaluated end-to-end on the test set, even though the evaluation framework in Section III-C supports such a test. Since hls4ml does not guarantee bit-exact equivalence with floating point and recurrent accumulation over 15 time steps can amplify fixed-point errors, the conclusion in Section V that the compression combination 'maintains performance' is unsupported. Please add a hardware-in-the-loop accuracy measurement or clearly state that Table II corresponds only to the software model.
  2. [Section IV-B and Table II] The reported size of 3.40 KB for 871 parameters equals 4 bytes per parameter, i.e., float32, despite the statement in Section IV-B that post-quantization with 8-bit fixed-point precision is applied. The 45.90x compression ratio is therefore a parameter-count ratio rather than the memory footprint of the model actually deployed. Please report the quantized model's weight and bias footprint in bytes and recompute the compression ratio from that footprint.
  3. [Section IV-C, Table III] The latency and power comparisons are presented as single numbers with no measurement variability or repetition. For example, LSTM-DO-S at 2.82 us and 0.887 W versus Split-B at 3.54 us and 0.829 W are the basis for the claimed trade-off, but without repeated measurements or error bars it is unclear whether these differences are significant given the digital multimeter and timing methodology. Please provide repeated measurements or state the number of trials and the observed spread.
  4. [Section IV-A and Section V] The time-series test split is not described as chronological. For daily water-quality measurements, a random 70/30 split would leak future information into training and could inflate the reported R2 values. Please specify whether the split respects temporal order and, if it does not, re-evaluate the models with a temporal split.
  5. [Section III-A and Section V] The split-learning communication aspect is not evaluated. The paper assumes ideal channel conditions and reports only on-chip FPGA metrics; no end-to-end split inference latency, bandwidth, or energy for the edge-server link is measured. The conclusion about the potential of split learning on resource-limited hardware therefore rests on FPGA-only results. Either add a communication-cost measurement or temper the conclusion to cover only FPGA acceleration of the edge sub-network.
minor comments (5)
  1. [Section II-B, reference [3]] The text refers to 'Bertel et al. [3]' but the reference entry is 'J. Bartels et al.'; please correct the author name.
  2. [Section III-B, Eq. (1)] In Eq. (1), the notation is inconsistent: MSETL and MSETS are used without separate definitions, and the sentence 'MSE TL defined as...' contains an odd typographical break. Please define both terms cleanly.
  3. [Table I] The teacher's loss function is listed as 'LMSE' without a definition; please state that it is the standard mean squared error used for regression.
  4. [Section IV-C, Table III] The 'Overall max utilization' row is not defined, and it is not derived from the scalability formula given for SC. Please explain how this value is computed.
  5. [Section IV-B] The paper states that the student architecture is chosen heuristically to reduce communication overhead and that a deeper architecture is preferred, but no procedure or reference is given for this design choice; please add a brief justification.

Circularity Check

0 steps flagged · score 2.0 of 10

No load-bearing circularity: the resource, latency, and power results are measured externally, and the reused self-cited workflow [32] is methodological rather than a derivation that forces the conclusions.

full rationale

The paper is an empirical deployment study rather than a derivation chain. The teacher/student accuracies in Table II (Section IV-C) are trained model metrics; the FPGA resource, latency, power, and scalability figures in Table III are hardware measurements on a Basys 3 Artix-7 FPGA (Section IV-C), so they do not reduce to any fitted parameter or to an equation in the paper. Eq. (1) is a standard distillation loss with a hand-set alpha = 0.1 (Table I); it defines the training objective and does not, by construction, predict any reported hardware result. The 45.90x compression ratio is arithmetic from Table II (39,951 vs. 871 parameters; 156.06 KB vs. 3.40 KB) and is not a fitted 'prediction' dressed up as a finding. The self-citations are non-load-bearing: [32] is cited only as an adapted compression/deployment workflow ('we adapted the workflow proposed in [32]'), [22] is mentioned as prior communication-aware work but the current study explicitly assumes ideal channel conditions, and [21] is declared out of scope. None of these supplies an unverified theorem or an ansatz that forces the outcome. Two evidence gaps should nevertheless be flagged explicitly, though they are not circularity: (i) Table II reports only software student metrics, so the Section V claim that the KD/P/Q combination offers 'faster forecasting and improved memory efficiency, while maintaining performance' is not verified for the deployed hls4ml accelerator, whose end-to-end fixed-point accuracy is never measured; and (ii) the reported 3.40 KB for 871 parameters corresponds to 4 bytes/parameter, i.e., float32, so the stated 8-bit post-quantization size is not actually reported. These are missing validations, not circular reductions. Overall circularity is minimal, warranting score 2 only for the non-load-bearing reuse of the authors' own workflow [32].

Assumptions & free parameters 4 free parameters · 4 assumptions · 0 invented entities

The paper makes no first-principles derivation; it is an empirical deployment study. The central measurements depend on several hand-chosen hyperparameters (alpha=0.1, 70% sparsity, 8-bit quantization, unspecified student hidden sizes) and on the stated assumption of ideal channel conditions. No new entities are invented, and no falsifiable prediction is made outside the reported board-specific measurements.

free parameters (4)
  • Distillation weight alpha = 0.1
    Table I sets alpha=0.1 in Eq. (1) to weight true-label vs teacher-soft-target MSE; chosen manually, affects student accuracy and hardware footprint.
  • Pruning target sparsity = 70%
    Post-pruning applied with a target sparsity of 70% (Section IV-B), likely set by hand; affects model size and accuracy.
  • Quantization precision = 8-bit fixed point
    Post-quantization with 8-bit fixed-point precision (Section IV-B), chosen manually; directly affects BRAM/FF usage and possibly accuracy.
  • Student hidden-layer sizes = not reported
    The student architecture is 'heuristically tuned' (Section III-B) to reduce communication overhead; the numerical hidden dimensions are not given, yet they determine parameter count (871) and intermediate output sizes (5 and 150).
assumptions (4)
  • domain assumption Ideal channel conditions between buoy and server
    Section III-A explicitly assumes ideal channel conditions; this removes communication latency/error from the split inference evaluation.
  • domain assumption The Danube dataset is representative for dissolved oxygen forecasting and the 70/30 split is faithful
    Section IV-A; no leakage analysis or cross-validation is reported, and the dataset is not released.
  • domain assumption hls4ml and ComBlock correctly implement the LSTM in hardware
    The paper relies on these toolchains (Section III-B/III-C) without independent verification of bit-exactness against the software model.
  • standard math Mean squared error is an appropriate distillation loss for regression
    Eq. (1) replaces KL divergence with MSE following [33]; this is a standard choice for regression KD, invoked without derivation.

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Pith. "Pith review of Efficient Split Learning LSTM Models for FPGA-based Edge IoT Devices." pith.science (2026). https://pith.science/paper/DQWXPC2G

@misc{pith2026250208692,
  author       = {Pith},
  title        = {Pith review of: Efficient Split Learning LSTM Models for FPGA-based Edge IoT Devices},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/DQWXPC2G}},
  note         = {Machine review of arXiv:2502.08692}
}
read the original abstract

Split Learning (SL) recently emerged as an efficient paradigm for distributed Machine Learning (ML) suitable for the Internet Of Things (IoT)-Cloud systems. However, deploying SL on resource-constrained edge IoT platforms poses a significant challenge in terms of balancing the model performance against the processing, memory, and energy resources. In this work, we present a practical study of deploying SL framework on a real-world Field-Programmable Gate Array (FPGA)-based edge IoT platform. We address the SL framework applied to a time-series processing model based on Recurrent Neural Networks (RNNs). Set in the context of river water quality monitoring and using real-world data, we train, optimize, and deploy a Long Short-Term Memory (LSTM) model on a given edge IoT FPGA platform in different SL configurations. Our results demonstrate the importance of aligning design choices with specific application requirements, whether it is maximizing speed, minimizing power, or optimizing for resource constraints.

Figures

Figures reproduced from arXiv: 2502.08692 by the authors.

Figure 1
Figure 1. Split learning/inference pipeline with edge and server sub–networks [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. IoT-based water quality monitoring system with a) smart buoy with [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Knowledge distillation Pruning Quantization keras model (.h5) hls4ml HLS porject Hardware evaluation framework MicroBlaze Communication block UART LSTM accelerator Integration with a hardware synthesis tool for ML LSTM training and compression Compressed model LSTM accelerator [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figures from the paper (1 more)
Figure 4
Figure 4. Figure 4: Hardware evaluation framework. IV. PERFORMANCE EVALUATION A. Dataset Generation The dataset utilized in this study for IoT-based water quality monitoring provides a comprehensive foundation for assessing river health and identifying potential pollution. Collected from …

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