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UB-Mesh: a Hierarchically Localized nD-FullMesh Datacenter Network Architecture

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arxiv 2503.20377 v3 pith:BRN6XW3Y submitted 2025-03-26 cs.AR cs.NI

classification cs.ARcs.NI
keywords architectureub-meshdesignnetworkbandwidthdatand-fullmeshtopology
verification ladder T0 review T1 audit T2 compute T3 formal
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As the Large-scale Language Models (LLMs) continue to scale, the requisite computational power and bandwidth escalate. To address this, we introduce UB-Mesh, a novel AI datacenter network architecture designed to enhance scalability, performance, cost-efficiency and availability. Unlike traditional datacenters that provide symmetrical node-to-node bandwidth, UB-Mesh employs a hierarchically localized nD-FullMesh network topology. This design fully leverages the data locality of LLM training, prioritizing short-range, direct interconnects to minimize data movement distance and reduce switch usage. Although UB-Mesh's nD-FullMesh topology offers several theoretical advantages, its concrete architecture design, physical implementation and networking system optimization present new challenges. For the actual construction of UB-Mesh, we first design the UB-Mesh-Pod architecture, which is based on a 4D-FullMesh topology. UB-Mesh-Pod is implemented via a suite of hardware components that serve as the foundational building blocks, including specifically-designed NPU, CPU, Low-Radix-Switch (LRS), High-Radix-Switch (HRS), NICs and others. These components are interconnected via a novel Unified Bus (UB) technique, which enables flexible IO bandwidth allocation and hardware resource pooling. For networking system optimization, we propose advanced routing mechanism named All-Path-Routing (APR) to efficiently manage data traffic. These optimizations, combined with topology-aware performance enhancements and robust reliability measures like 64+1 backup design, result in 2.04x higher cost-efficiency, 7.2% higher network availability compared to traditional Clos architecture and 95%+ linearity in various LLM training tasks.

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Cited by 3 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. StrataCL: Fabric-Native Communication Library for Production Supernodes

    cs.DC 2026-07 conditional novelty 6.0 of 10

    On Huawei CloudMatrix384, StrataCL's registration-on-allocation and fabric-native operators raise collective bus bandwidth up to 1.6x and LLM inference throughput by 1.9x versus HCCL baselines.

  2. TENT: A Declarative Slice Spraying Engine for Performant and Resilient Data Movement in Disaggregated LLM Serving

    cs.DC 2026-04 conditional novelty 6.0 of 10

    A telemetry-driven slice-spraying transfer engine with late-binding path selection improves LLM serving throughput and self-heals from link failures in tens of milliseconds.

  3. Serving Large Language Models on Huawei CloudMatrix384

    cs.DC 2025-06 conditional novelty 6.0 of 10

    CloudMatrix384 with CloudMatrix-Infer reports prefill 6,688 tokens/s per NPU and decode 1,943 tokens/s per NPU on DeepSeek-R1, exceeding published NVIDIA-based efficiencies.

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