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REVIEW 5 major objections 5 minor 1 cited by

iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMs

T0 review · 5 major / 5 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read An LLM-guided search matches NSGA-II with only 4.6% of the designs in HLS exploration.

desk verdict A promising LLM-guided HLS DSE pipeline whose headline numbers are measured against a pruned-space reference front; the unproved pruning-preservation claim is the key thing to check. read the letter →

arxiv 2505.22086 v2 pith:HVCXXN47 submitted 2025-05-28 cs.AR cs.AI

Runkai Li , Jia Xiong , Xi Wang This is my paper
classification cs.ARcs.AI
keywords high-levelsynthesisdesignspaceexplorationlargelanguagemodelsParetofrontoptimizationdirectivesmultiobjectiveFPGAwarm-startinitialization
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper tries to establish that a large language model, given a pruned HLS directive space and real synthesis feedback, can steer high-level-synthesis design space exploration to near-reference Pareto fronts using very few HLS runs. The authors build iDSE around three stages: rule-based plus LLM-assisted pruning of invalid or redundant directive combinations, LLM-generated seed configurations that warm-start the population, and an adaptive loop that alternates convergent bottleneck-driven tuning with divergent refactoring. Reported results say iDSE gets 5.1x to 16.6x closer to the reference Pareto front than heuristic baselines and reaches NSGA-II-quality fronts with only 4.6% of the explored designs. A reader should care because HLS synthesis evaluations are the dominant cost, so shifting cost from many black-box iterations to a few informed prompts could make accelerator exploration practical without training a surrogate model.

What carries the argument

The machinery is a three-stage pipeline built on a structured directive feature vector. Feature-Driven Pruning compresses the design space by rule- and LLM-based elimination of aggressive or redundant parallelism; Seed Directive Generation uses LLM prior knowledge to produce diverse warm-start configurations; and QoR-Aware Adaptive Optimization labels the population by non-dominated rank and crowding distance, then uses bottleneck analysis for oriented tuning and divergence-enhanced refactoring for non-oriented tuning. The feature vector encoding pipeline, unroll, and array-partition choices is what lets the LLM reason about configurations without carrying raw HLS semantics.

What would settle it

Enumerate a small benchmark exhaustively, compute the true Pareto front over the full directive space, apply the pruning rules, and check whether any true Pareto-optimal configuration is missing from the pruned space; if one is missing, the ADRS reported inside the pruned space is overstated relative to the original problem.

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Extended reading notes

Core claim

The central claim is that LLM priors plus lightweight structural pruning can replace most of the trial-and-error in HLS design space exploration. Instead of letting a generic optimizer search the Cartesian product of pipeline, unroll, and array-partition directives, iDSE first extracts loop and array structure, prunes configurations that are invalid or redundant, asks the LLM to sample twelve representative seed configurations spanning performance-first, resource-first, and balanced regions, and then iteratively reflects on synthesis quality to produce both convergent refinements and divergent alternatives. On twelve benchmarks spanning PolyBench, CHStone, and MachSuite, the paper reports geometric-mean ADRS improvements of 16.6x over NSGA-II and 5.1x over HGBO-DSE, and claims that with under fifty synthesis evaluations the explored fronts are broader and more concave than those of baseline methods. The paper also argues that the LLM-generated seed designs are the main driver: single-batch warm start alone reaches the target ADRS, and plugging these seeds into NSGA-II and MOEA/D improves their final ADRS.

Load-bearing premise

The load-bearing premise is that the hand-written pruning rules, with LLM assistance, remove only invalid or redundant directive configurations and never remove a true Pareto-optimal design.

Editorial extensions

If this is right

  • With few HLS synthesis calls, designers can obtain a front spanning latency and utilization trade-offs without training a surrogate model.
  • Heuristic DSE methods inherit the warm-start benefit: NSGA-II and MOEA/D improve notably when initialized with LLM seeds instead of random, Beta, or Latin-hypercube sampling.
  • Invalid configurations that would waste synthesis time can be filtered before any HLS evaluation, reducing failed or timed-out runs by 89.9% in the ablation.
  • The approach is LLM-agnostic in principle: the paper shows different general-purpose LLMs all drive improvement, with no single model dominating across benchmarks.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Rebuilding the reference Pareto front from the unpruned design space would directly test whether the pruning rules preserve all true Pareto-optimal configurations.
  • The near-4.6% efficiency figure depends on comparing against a reference front built inside the pruned space, so the preservation question is the key check on the headline claim.
  • A testable extension is to ablate convergent and divergent tuning separately across benchmark families, since the paper's ablation bundles them together.
  • Because seed quality alone reaches the target ADRS in all benchmarks, seed-generation prompts and the choice of LLM are likely the highest-leverage component, and a cheaper, smaller model might capture much of the gain.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

5 major / 5 minor

Summary. The paper presents iDSE, an LLM-guided design space exploration framework for High-Level Synthesis. The pipeline has three stages: a Feature-Driven Pruning step that removes directive configurations deemed invalid or redundant, an LLM-based warm-start that generates initial seed directive configurations, and a QoR-aware adaptive optimization loop in which the LLM performs trajectory reflection, bottleneck analysis, and divergent design refactoring. The authors evaluate iDSE on 12 benchmarks from PolyBench, MachSuite, and CHStone using Vitis HLS on a Xilinx ZCU106 board, comparing against NSGA-II, ACO, MOEA/D, Lattice, and HGBO-DSE. The central reported result is a geometric-mean ADRS improvement of 5.1x to 16.6x over heuristic DSE baselines, with iDSE matching NSGA-II using approximately 4.6% of the explored designs.

Significance. If the reported results hold, iDSE would be a notable demonstration that LLM priors, combined with light-weight pruning and a small number of real HLS synthesis evaluations, can approximate multiobjective Pareto fronts in HLS design space exploration. The paper contains several strengths: the framework is evaluated with real HLS synthesis rather than a surrogate model; the warm-start ablation in Table 3 is a useful internal control showing that LLM-generated initial seeds often accelerate evolutionary DSE; the ablation in Figure 6 quantifies the contribution of pruning and trajectory reflection; and the prompts are stated to be benchmark-agnostic. These are credible and worth publishing if the load-bearing assumptions are verified. However, the headline claims currently rest on an unproved preservation property of the pruning step and on comparisons that omit the very LLM-based DSE systems cited in the related work. The significance is therefore conditional on closing those gaps.

major comments (5)
  1. [§4.1, §5.1, Appendix A.2] The load-bearing claim that Feature-Driven Pruning 'preserves potential Pareto-optimal designs' (Section 4.1) is unproved, and every ADRS value in Table 1 is measured against a reference front constructed in the pruned space, as stated in Section 5.1. The pruning rules in Appendix A.2 eliminate entire configuration classes (e.g., inner-loop unroll set to 0 for imperfect loops, outer-loop unroll set to 0 for 3+ level nested loops, outer-loop pipeline disabled when the inner trip count exceeds 32). If any of these classes contains nondominated designs in the original objective space, the reference front is incomplete and the reported 5.1x-16.6x improvements are overstated relative to the original design space. The authors should verify preservation concretely, for example by exhaustively enumerating the small benchmarks (stencil2d, sha, autocorr) both with and without pruning and reporting whether any Pareto-optimal design is lost, or by providing a formal argument that the pruning rules never remove nondominated configurations.
  2. [§5.1, Table 1] The experimental comparison omits the LLM-based DSE baselines that the paper itself cites, including LLM-DSE [63] and Intelligent4DSE [85]. The paper's abstract and introduction claim the 'first LLM-aided DSE framework', but the evaluation in Table 1 compares only NSGA-II, ACO, MOEA/D, Lattice, and HGBO-DSE. Given that the contribution is specifically an LLM-navigated approach, the central claim requires either a direct comparison with existing LLM-based DSE methods or an explicit, justified statement of why those baselines are not included. Without this, the claimed improvement over 'heuristic-based DSE methods' is accurate but the broader significance claim is not fully supported.
  3. [Table 1, Table 3, Table 8] The main ADRS results in Table 1 are reported without variance or statistical significance. LLM inference is stochastic, HLS synthesis can have nondeterministic effects, and Table 3 notes that only some numbers are averages over 5 runs (with warm-start being the average of 5 DeepSeek-R1 invocations). The central performance claim, a geometric-mean improvement of 16.6x over NSGA-II and 5.1x over HGBO-DSE, should be accompanied by confidence intervals or a statistical test over repeated runs. The current presentation does not allow a reader to judge whether the reported differences are robust to sampling noise.
  4. [Table 3, §5.2] The claim in Section 5.2 that 'ADRS drops substantially when seed designs more accurately approximate the reference Pareto fronts' is contradicted by the autocorr row of Table 3, where NSGA-II with Warm-Start has ADRS 0.7458 versus 0.0883 with Random Sampling and 0.0702 with Beta Sampling. Table 10 shows the same pattern after the search phase (0.1521 for Warm-Start versus 0.0913 for Random Sampling). The paper should acknowledge this exception and explain why the warm-start can degrade performance on some benchmarks, rather than stating a universal improvement.
  5. [Appendix D.5] The paper states that code and data will be uploaded 'after publication' but does not release an artifact for review. Given the strong empirical claims and the dependency on LLM prompts, API versions, and Vitis HLS settings, the absence of a complete artifact is a significant reproducibility concern. The authors should provide the full implementation, prompts, generated Tcl scripts, raw QoR reports, and a versioned configuration of the toolchain, or at least make them available for the review process.
minor comments (5)
  1. [Abstract] The abstract contains a typo: 'pruns' should be 'prunes'.
  2. [§3, Eq. (3)] The definition of ADRS in Definition 3 refers to a distance function d(·) that is not defined until Eq. (5) in Appendix C.1; defining d in the main text would make the metric self-contained.
  3. [Eq. (6)] The utilization weighting coefficients (W_LUT=0.3, W_FF=0.25, W_DSP=0.3, W_BRAM=0.05) are presented without sensitivity analysis or a citation. Since they define the objective space used for Pareto dominance, their choice can affect the conclusions; a brief robustness check would strengthen the paper.
  4. [§1, §2] The phrase 'the first LLM-aided DSE framework' appears in the introduction and abstract, yet the related work cites LLM-DSE [63] and Intelligent4DSE [85]. The novelty statement should be softened to acknowledge these contemporaneous efforts and to specify the precise distinction (e.g., end-to-end QoR perception, pruning, and warm-start).
  5. [Figure 15, Table 2] Several figures and tables appear with corrupted or garbled text in the preprint version (e.g., Figure 15's axis labels and Table 2's benchmark-group column). These should be cleaned up in the final version for readability.

Circularity Check

0 steps flagged · score 2.0 of 10

No circular derivation: ADRS targets are independently synthesized, all methods share the same pruned space, and self-citations are confined to related work.

full rationale

I find no circular step in the claimed derivation chain. The ADRS reference fronts are constructed by random sampling, breadth-first search, or exhaustive exploration with the Vitis HLS synthesis tool (Section 5.1), not from iDSE's own outputs, and all compared methods—including iDSE—explore the same Feature-Driven-Pruned design space, so the relative comparisons do not reduce to the framework's own predictions. The Warm-Start and Adaptive Optimization components are evaluated through measured latency and utilization from HLS synthesis, not by fitting a parameter to the ADRS values. Self-citations of the corresponding author's earlier LLM/EDA papers (ChatCPU, MEIC, UVLLM, VGV, VeriDebug, etc.) appear only in the related-work survey and supply no load-bearing premise, uniqueness theorem, or fitted ansatz. The unproved Section 4.1 assertion that Feature-Driven Pruning 'preserves potential Pareto-optimal designs' is a genuine correctness and external-validity risk, because the reference front is built inside the pruned space; however, it is not a circularity: even if the pruning rules removed true Pareto-optimal designs, the reported numbers would be biased relative to the original space, not equivalent by construction to the paper's inputs. No equation is defined in terms of the quantity it purports to derive, and no fitted value is renamed as a prediction.

Assumptions & free parameters 4 free parameters · 4 assumptions · 0 invented entities

All reported metrics depend on hand-chosen evaluation weights, pruning rules, and search hyperparameters; the paper provides no sensitivity analysis for the weights or the pruning rules. The central assumptions are the HLS synthesis oracle, the preservation of optimal designs by pruning, the transfer of LLM prior knowledge, and the completeness of the reference front; none has an independent proof in the paper.

free parameters (4)
  • Utilization weights W_LUT, W_FF, W_DSP, W_BRAM = 0.3, 0.25, 0.3, 0.05
    Chosen by hand in Eq. 6 (Appendix C.1) to define the utilization objective; all ADRS comparisons depend on this weighting, and no sensitivity analysis is provided.
  • Pruning thresholds in Feature-Driven Pruning = e.g., outer loop pipeline off if inner trip count > 32; unroll factors as powers of 2; outermost unroll off for 3+…
    Hand-coded rules in Appendix A.2 and prompts B.2 and B.4; they determine the pruned design space searched by every method, and the claim that they preserve Pareto-optimal designs is unproved.
  • Initial sample size N0 = 12
    Selected in Appendix D.1 by a trade-off plot; affects warm-start quality and all efficiency results.
  • Adaptive optimization generations Imax = 3
    Hyperparameter Table 5, Appendix A.4; tuning this limit changes the Pareto front quality and search budget.
assumptions (4)
  • domain assumption HLS synthesis reports from Vitis HLS 2022.1 are a faithful oracle for latency and utilization.
    Used implicitly throughout Section 5; no verification of functional correctness or routing-level performance is performed.
  • ad hoc to paper Feature-Driven Pruning preserves all Pareto-optimal designs in the original space.
    Asserted in Section 4.1 and Appendix A.2, but no proof or measurement is given.
  • domain assumption LLM pretraining contains transferable HLS optimization knowledge that can be elicited via the supplied prompts.
    Central to warm-start and adaptive optimization; the paper shows correlations but does not isolate this assumption from benchmark-specific leakage.
  • domain assumption The reference Pareto fronts built by exhaustive search or random sampling plus BFS are complete enough for the ADRS comparison.
    Described in Section 5.1; for large design spaces the reference may miss regions that iDSE finds, affecting ADRS fairness.

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Cite this review

Pith. "Pith review of iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMs." pith.science (2026). https://pith.science/paper/HVCXXN47

@misc{pith2026250522086,
  author       = {Pith},
  title        = {Pith review of: iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMs},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/HVCXXN47}},
  note         = {Machine review of arXiv:2505.22086}
}
abstract

High-Level Synthesis (HLS) serves as an agile hardware development tool that streamlines the circuit design by abstracting the register transfer level into behavioral descriptions, while allowing designers to customize the generated microarchitectures through optimization directives. However, the combinatorial explosion of possible directive configurations yields an intractable design space. Traditional design space exploration (DSE) methods, despite adopting heuristics or constructing predictive models to accelerate Pareto-optimal design acquisition, still suffer from prohibitive exploration costs and suboptimal results. Addressing these concerns, we introduce iDSE, the first LLM-aided DSE framework that leverages HLS design quality perception to effectively navigate the design space. iDSE intelligently pruns the design space to guide LLMs in calibrating representative initial sampling designs, expediting convergence toward the Pareto front. By exploiting the convergent and divergent thinking patterns inherent in LLMs for hardware optimization, iDSE achieves multi-path refinement of the design quality and diversity. Extensive experiments demonstrate that iDSE outperforms heuristic-based DSE methods by 5.1$\times$$\sim$16.6$\times$ in proximity to the reference Pareto front, matching NSGA-II with only 4.6% of the explored designs. Our work demonstrates the transformative potential of LLMs in scalable and efficient HLS design optimization, offering new insights into multiobjective optimization challenges.

Figures

Figures reproduced from arXiv: 2505.22086 by the authors.

Figure 1
Figure 1. Time-consuming manual directive configuration tuning based on QoR reported in HLS. [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Example of customizing synthesized hardware with HLS optimization directives. [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. iDSE Workflow 4.1 Preprocessing: Directive Configuration Extraction and Design Space Pruning The allocation of loop and memory access parallelism constitutes a critical bottleneck in hardware op￾timization, significantly affecting both performance and resource utilization of synthesized hardware designs. Feature Extractor parses the design structure to extract key structural metadata (e.g., array dimensions, loop tr… view at source ↗
Figures from the paper (15 more)
Figure 4
Figure 4. Figure 4: Comparison of explored Pareto fronts across benchmarks with different design spaces. [PITH_FULL_IMAGE:figures/full_fig_p007_4.png]
Figure 5
Figure 5. Figure 5: Comparison among EA-based DSE methods under different initial sampling designs. [PITH_FULL_IMAGE:figures/full_fig_p008_5.png]
Figure 6
Figure 6. Figure 6: Ablation of Adaptive Optimization. The geometric mean improvement trend of ADRS in [PITH_FULL_IMAGE:figures/full_fig_p009_6.png]
Figure 7
Figure 7. Figure 7: Prompt for Feature Extractor. B.2 Prompt for Feature-Driven Pruning In [PITH_FULL_IMAGE:figures/full_fig_p019_7.png]
Figure 8
Figure 8. Figure 8: Prompt for Feature-Driven Pruning. B.3 Prompt for Seed Directive Generation [PITH_FULL_IMAGE:figures/full_fig_p020_8.png]
Figure 9
Figure 9. Figure 9: Prompt for Seed Directive Generation. B.4 Prompt for QoR-Aware Adaptive Optimization In this section, we present in detail the prompts in our QoR-Aware Adaptive Optimization system. In [PITH_FULL_IMAGE:figures/full_fig_p021_9.png]
Figure 10
Figure 10. Figure 10: Prompt for optimization trajectory reflection. [PITH_FULL_IMAGE:figures/full_fig_p021_10.png]
Figure 11
Figure 11. Figure 11: Prompt for bottleneck analysis with QoR-aware adaptation. [PITH_FULL_IMAGE:figures/full_fig_p022_11.png]
Figure 12
Figure 12. Figure 12: Prompt for divergence-enhanced design refactoring. [PITH_FULL_IMAGE:figures/full_fig_p022_12.png]
Figure 13
Figure 13. Figure 13: Optimal initial sample size selection for efficient Pareto front coverage [PITH_FULL_IMAGE:figures/full_fig_p025_13.png]
Figure 14
Figure 14. Figure 14: Comparison of Pareto fronts constructed by different initial sampling designs [PITH_FULL_IMAGE:figures/full_fig_p026_14.png]
Figure 15
Figure 15. Figure 15: Comparison of invalid design counts with and without Feature-Driven Pruning We provide supplementary data for [PITH_FULL_IMAGE:figures/full_fig_p028_15.png]
Figure 16
Figure 16. Figure 16: Comparison of ADRS among MOEA/D-based DSE method under different LLMs. [PITH_FULL_IMAGE:figures/full_fig_p028_16.png]
Figure 17
Figure 17. Figure 17: Comparison of ADRS among NSGA-II-based DSE method under different LLMs. [PITH_FULL_IMAGE:figures/full_fig_p029_17.png]
Figure 18
Figure 18. Figure 18: t-SNE visualization of reference Pareto-optimal and explored optimization directives in [PITH_FULL_IMAGE:figures/full_fig_p030_18.png]

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Reference graph

Works this paper leans on

96 extracted references · 65 canonical work pages · cited by 1 Pith paper

  1. [63]

    LLM-DSE: Searching accelerator parameters with LLM agents

    Hanyu Wang, Xinrui Wu, Zijian Ding, Su Zheng, Chengyue Wang, Tony Nowatzki, Yizhou Sun, and Jason Cong. LLM-DSE: Searching accelerator parameters with LLM agents. arXiv preprint arXiv:2505.12188, 2025

    arXiv 2025

  2. [85]

    Intelligent4DSE: Optimiz- ing high-level synthesis design space exploration with graph neural networks and large language models

    Lei Xu, Shanshan Wang, Emmanuel Casseau, and Chenglong Xiao. Intelligent4DSE: Optimiz- ing high-level synthesis design space exploration with graph neural networks and large language models. arXiv preprint arXiv:2504.19649, 2025

    work page arXiv 2025

  3. [1]

    Jouppi, Doe Hyun Yoon, Matthew Ashcraft, Mark Gottscho, Thomas B

    Norman P. Jouppi, Doe Hyun Yoon, Matthew Ashcraft, Mark Gottscho, Thomas B. Jablin, George Kurian, James Laudon, Sheng Li, Peter Ma, Ma, et al. Ten lessons from three generations shaped Google’s TPUv4i : Industrial product. In 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA), pages 1–14, 2021

    2021

  4. [2]

    Jouppi, Cliff Young, Nishant Patil, David Patterson, Gaurav Agrawal, Raminder Bajwa, Sarah Bates, Suresh Bhatia, Nan Boden, Borchers, et al

    Norman P. Jouppi, Cliff Young, Nishant Patil, David Patterson, Gaurav Agrawal, Raminder Bajwa, Sarah Bates, Suresh Bhatia, Nan Boden, Borchers, et al. In-datacenter performance analysis of a tensor processing unit. In 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), pages 1–12, 2017

    2017

  5. [3]

    Emer, and Vivienne Sze

    Yu-Hsin Chen, Tushar Krishna, Joel S. Emer, and Vivienne Sze. Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks. IEEE Journal of Solid-State Circuits, 52(1):127–138, 2017

    2017

  6. [4]

    Ashish Gondimalla, Noah Chesnut, Mithuna Thottethodi, and T. N. Vijaykumar. SparTen: A sparse tensor accelerator for convolutional neural networks. In Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), page 151–165, 2019

    2019

  7. [5]

    Fusion-3D: Integrated acceleration for instant 3D reconstruction and real-time rendering

    Sixu Li, Yang Zhao, Chaojian Li, Bowei Guo, Jingqun Zhang, Wenbo Zhu, Zhifan Ye, Cheng Wan, and Yingyan Celine Lin. Fusion-3D: Integrated acceleration for instant 3D reconstruction and real-time rendering. In2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO), pages 78–91, 2024

    2024

  8. [6]

    CamPU: A multi-camera processing unit for deep learning- based 3D spatial computing systems

    Dongseok Im and Hoi-Jun Yoo. CamPU: A multi-camera processing unit for deep learning- based 3D spatial computing systems. In 2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO), pages 50–63, 2024

    2024

Show all 96 references
  1. [7]

    Neuman, Radhika Ghosal, Thomas Bourgeat, Brian Plancher, and Vijay Janapa Reddi

    Sabrina M. Neuman, Radhika Ghosal, Thomas Bourgeat, Brian Plancher, and Vijay Janapa Reddi. RoboShape: Using topology patterns to scalably and flexibly deploy accelerators across robots. In Proceedings of the 50th Annual International Symposium on Computer Architecture (ISCA), 2023

    2023

  2. [8]

    Neuman, Brian Plancher, Thomas Bourgeat, Thierry Tambe, Srinivas Devadas, and Vijay Janapa Reddi

    Sabrina M. Neuman, Brian Plancher, Thomas Bourgeat, Thierry Tambe, Srinivas Devadas, and Vijay Janapa Reddi. Robomorphic computing: a design methodology for domain-specific accelerators parameterized by robot morphology. In Proceedings of the 26th ACM International Conference ...

    2021

  3. [9]

    BLESS: Bandwidth and locality enhanced smem seeding acceleration for DNA sequencing

    Seunghee Han, Seungjae Moon, Teokkyu Suh, JaeHoon Heo, and Joo-Young Kim. BLESS: Bandwidth and locality enhanced smem seeding acceleration for DNA sequencing. In 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA) , pages 582–596, 2024

    2024

  4. [10]

    QUETZAL: Vector acceleration framework for modern genome sequence analysis algorithms

    Julian Pavon, Ivan Vargas Valdivieso, Carlos Rojas, Cesar Hernandez, Mehmet Aslan, Roger Figueras, Yichao Yuan, Joël Lindegger, Mohammed Alser, Moll, et al. QUETZAL: Vector acceleration framework for modern genome sequence analysis algorithms. In 2024 ACM/IEEE 51st Annual Inte...

    2024

  5. [11]

    GMX: Instruction set extensions for fast, scalable, and efficient genome sequence alignment

    Max Doblas, Oscar Lostes-Cazorla, Quim Aguado-Puig, Nick Cebry, Pau Fontova-Musté, Christopher Frances Batten, Santiago Marco-Sola, and Miquel Moretó. GMX: Instruction set extensions for fast, scalable, and efficient genome sequence alignment. In Proceedings of the 56th Annual...

    2023

  6. [12]

    Kalsi, Ziyi Zuo, Can Firtina, Meryem Banu Cavlak, Jeremie Kim, Nika Mansouri Ghiasi, Singh, et al

    Damla Senol Cali, Konstantinos Kanellopoulos, Joël Lindegger, Zülal Bingöl, Gurpreet S. Kalsi, Ziyi Zuo, Can Firtina, Meryem Banu Cavlak, Jeremie Kim, Nika Mansouri Ghiasi, Singh, et al. SeGraM: a universal hardware accelerator for genomic sequence-to-graph and sequence-to-seq...

    2022

  7. [13]

    Amant, Karthikeyan Sankaralingam, and Doug Burger

    Hadi Esmaeilzadeh, Emily Blem, Renee St. Amant, Karthikeyan Sankaralingam, and Doug Burger. Dark silicon and the end of multicore scaling. IEEE Micro, 32(3):122–134, 2012. 10

    2012

  8. [14]

    Democratizing domain-specific computing

    Yuze Chi, Weikang Qiao, Atefeh Sohrabizadeh, Jie Wang, and Jason Cong. Democratizing domain-specific computing. Communications of the ACM, 66(1):74–85, 2022

    2022

  9. [15]

    High-Level Synthesis for FPGAs: From prototyping to deployment

    Jason Cong, Bin Liu, Stephen Neuendorffer, Juanjo Noguera, Kees Vissers, and Zhiru Zhang. High-Level Synthesis for FPGAs: From prototyping to deployment. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30(4):473–491, 2011

    2011

  10. [16]

    FPGA HLS today: Successes, challenges, and opportunities

    Jason Cong, Jason Lau, Gai Liu, Stephen Neuendorffer, Peichen Pan, Kees Vissers, and Zhiru Zhang. FPGA HLS today: Successes, challenges, and opportunities. ACM Transactions on Reconfigurable Technology and Systems, 15(4), 2022

    2022

  11. [17]

    Adaptive simulated annealer for high level synthesis design space exploration

    Benjamin Carrion Schafer, Takashi Takenaka, and Kazutoshi Wakabayashi. Adaptive simulated annealer for high level synthesis design space exploration. In 2009 International Symposium on VLSI Design, Automation and Test, pages 106–109, 2009

    2009

  12. [18]

    Parallel high-level synthesis design space exploration for behav- ioral IPs of exact latencies

    Benjamin Carrion Schafer. Parallel high-level synthesis design space exploration for behav- ioral IPs of exact latencies. ACM Transactions on Design Automation of Electronic Systems (TODAES), 22(4), 2017

    2017

  13. [19]

    Probabilistic multiknob high-level synthesis design space exploration acceleration

    Benjamin Carrion Schafer. Probabilistic multiknob high-level synthesis design space exploration acceleration. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 35(3):394–406, 2016

    2016

  14. [20]

    Correlated multi-objective multi-fidelity optimization for HLS directives design

    Qi Sun, Tinghuan Chen, Siting Liu, Jianli Chen, Hao Yu, and Bei Yu. Correlated multi-objective multi-fidelity optimization for HLS directives design. ACM Transactions on Design Automation of Electronic Systems (TODAES), 27(4), 2022

    2022

  15. [21]

    Lattice-traversing design space explo- ration for high level synthesis

    Lorenzo Ferretti, Giovanni Ansaloni, and Laura Pozzi. Lattice-traversing design space explo- ration for high level synthesis. In 2018 IEEE 36th International Conference on Computer Design (ICCD), pages 210–217, 2018

    2018

  16. [22]

    S2FA: An accelerator automation framework for heterogeneous computing in datacenters

    Cody Hao Yu, Peng Wei, Max Grossman, Peng Zhang, Vivek Sarker, and Jason Cong. S2FA: An accelerator automation framework for heterogeneous computing in datacenters. In 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), pages 1–6, 2018

    2018

  17. [23]

    Towards a comprehensive benchmark for high-level synthesis targeted to FPGAs

    Yunsheng Bai, Atefeh Sohrabizadeh, Zongyue Qin, Ziniu Hu, Yizhou Sun, and Jason Cong. Towards a comprehensive benchmark for high-level synthesis targeted to FPGAs. InProceedings of the 37th International Conference on Neural Information Processing Systems, 2023

    2023

  18. [24]

    Automated accelerator optimization aided by graph neural networks

    Atefeh Sohrabizadeh, Yunsheng Bai, Yizhou Sun, and Jason Cong. Automated accelerator optimization aided by graph neural networks. In Proceedings of the 59th ACM/IEEE Design Automation Conference (DAC), page 55–60, 2022

    2022

  19. [25]

    Robust GNN-Based representation learning for HLS

    Atefeh Sohrabizadeh, Yunsheng Bai, Yizhou Sun, and Jason Cong. Robust GNN-Based representation learning for HLS. In 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), pages 1–9, 2023

    2023

  20. [26]

    IronMan-Pro: Multiobjective design space exploration in HLS via reinforcement learning and graph neural network-based modeling

    Nan Wu, Yuan Xie, and Cong Hao. IronMan-Pro: Multiobjective design space exploration in HLS via reinforcement learning and graph neural network-based modeling. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 42(3):900–913, 2023

    2023

  21. [27]

    COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications

    Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, and Bingsheng He. COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications. In 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) , pages 430–437, 2017

    2017

  22. [28]

    Lin-Analyzer: A high- level performance analysis tool for FPGA-based accelerators

    Guanwen Zhong, Alok Prakash, Yun Liang, Tulika Mitra, and Smail Niar. Lin-Analyzer: A high- level performance analysis tool for FPGA-based accelerators. In 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), pages 1–6, 2016

    2016

  23. [29]

    Graph neural networks for high-level synthesis design space exploration

    Lorenzo Ferretti, Andrea Cini, Georgios Zacharopoulos, Cesare Alippi, and Laura Pozzi. Graph neural networks for high-level synthesis design space exploration. ACM Transactions on Design Automation of Electronic Systems (TODAES), 28(2), 2022. 11

    2022

  24. [30]

    Learning to compare hardware designs for high- level synthesis

    Yunsheng Bai, Atefeh Sohrabizadeh, Zijian Ding, Rongjian Liang, Weikai Li, Ding Wang, Haoxing Ren, Yizhou Sun, and Jason Cong. Learning to compare hardware designs for high- level synthesis. In 2024 ACM/IEEE 6th Symposium on Machine Learning for CAD (MLCAD), pages 1–7, 2024

    2024

  25. [31]

    HGBO-DSE: Hierarchical gnn and bayesian optimization based hls design space exploration

    Huizhen Kuang, Xianfeng Cao, Jingyuan Li, and Lingli Wang. HGBO-DSE: Hierarchical gnn and bayesian optimization based hls design space exploration. In 2023 International Conference on Field Programmable Technology (ICFPT), pages 106–114, 2023

    2023

  26. [32]

    ChatCPU: An agile CPU design and verification platform with LLM

    Xi Wang, Gwok-Waa Wan, Sam-Zaak Wong, Layton Zhang, Tianyang Liu, Qi Tian, and Jianmin Ye. ChatCPU: An agile CPU design and verification platform with LLM. In Proceedings of the 61st ACM/IEEE Design Automation Conference (DAC), 2024

    2024

  27. [33]

    MEIC: Re-thinking RTL debug automation using LLMs

    Ke Xu, Jialin Sun, Yuchen Hu, Xinwei Fang, Weiwei Shan, Xi Wang, and Zhe Jiang. MEIC: Re-thinking RTL debug automation using LLMs. In Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2025

    2025

  28. [34]

    ChatEDA: A large language model powered autonomous agent for EDA

    Haoyuan Wu, Zhuolun He, Xinyun Zhang, Xufeng Yao, Su Zheng, Haisheng Zheng, and Bei Yu. ChatEDA: A large language model powered autonomous agent for EDA. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 43(10):3184–3197, 2024

    2024

  29. [35]

    RTLFixer: Automatically fixing RTL syntax errors with large language model

    Yunda Tsai, Mingjie Liu, and Haoxing Ren. RTLFixer: Automatically fixing RTL syntax errors with large language model. In Proceedings of the 61st ACM/IEEE Design Automation Conference (DAC), 2024

    2024

  30. [36]

    GPT4AIGChip: Towards next-generation AI accelerator design automation via large language models

    Yonggan Fu, Yongan Zhang, Zhongzhi Yu, Sixu Li, Zhifan Ye, Chaojian Li, Cheng Wan, and Yingyan Celine Lin. GPT4AIGChip: Towards next-generation AI accelerator design automation via large language models. In 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD...

    2023

  31. [37]

    Large language models as optimizers

    Chengrun Yang, Xuezhi Wang, Yifeng Lu, Hanxiao Liu, Quoc V Le, Denny Zhou, and Xinyun Chen. Large language models as optimizers. arXiv preprint arXiv:2309.03409, 2023

    2023 arXiv

  32. [38]

    Large language models as evolutionary optimizers

    Shengcai Liu, Caishun Chen, Xinghua Qu, Ke Tang, and Yew-Soon Ong. Large language models as evolutionary optimizers. In 2024 IEEE Congress on Evolutionary Computation (CEC), pages 1–8, 2024

    2024

  33. [39]

    Exploring the true potential: Evaluating the black-box optimization capability of large language models

    Beichen Huang, Xingyu Wu, Yu Zhou, Jibin Wu, Liang Feng, Ran Cheng, and Kay Chen Tan. Exploring the true potential: Evaluating the black-box optimization capability of large language models. arXiv preprint arXiv:2404.06290, 2024

    2024 arXiv

  34. [40]

    Large language models to enhance bayesian optimization

    Tennison Liu, Nicolás Astorga, Nabeel Seedat, and Mihaela van der Schaar. Large language models to enhance bayesian optimization. arXiv preprint arXiv:2402.03921, 2024

    2024 arXiv

  35. [41]

    Evolutionary com- putation in the era of large language model: Survey and roadmap

    Xingyu Wu, Sheng-Hao Wu, Jibin Wu, Liang Feng, and Kay Chen Tan. Evolutionary com- putation in the era of large language model: Survey and roadmap. IEEE Transactions on Evolutionary Computation, 29(2):534–554, 2025

    2025

  36. [42]

    Efficient task transfer for HLS DSE

    Zijian Ding, Atefeh Sohrabizadeh, Weikai Li, Zongyue Qin, Yizhou Sun, and Jason Cong. Efficient task transfer for HLS DSE. In Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2025

    2025

  37. [43]

    AutoDSE: Enabling software programmers to design efficient FPGA accelerators

    Atefeh Sohrabizadeh, Cody Hao Yu, Min Gao, and Jason Cong. AutoDSE: Enabling software programmers to design efficient FPGA accelerators. ACM Transactions on Design Automation of Electronic Systems (TODAES), 27(4), 2022

    2022

  38. [44]

    Design space exploration of multiple loops on fpgas using high level synthesis

    Guanwen Zhong, Vanchinathan Venkataramani, Yun Liang, Tulika Mitra, and Smail Niar. Design space exploration of multiple loops on fpgas using high level synthesis. In 2014 IEEE 32nd International Conference on Computer Design (ICCD), pages 456–463, 2014

    2014

  39. [45]

    Exploiting loop-array dependencies to accelerate the design space exploration with high level synthesis

    Nam Khanh Pham, Amit Kumar Singh, Akash Kumar, and Mi Mi Aung Khin. Exploiting loop-array dependencies to accelerate the design space exploration with high level synthesis. In 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 157–162, 2015. 12

    2015

  40. [46]

    A unified framework for automated code transformation and pragma insertion

    Stéphane Pouget, Louis-Noël Pouchet, and Jason Cong. A unified framework for automated code transformation and pragma insertion. In Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), page 187–198, 2025

    2025

  41. [47]

    Automatic hardware pragma insertion in high-level synthesis: A non-linear programming approach

    Stéphane Pouget, Louis-Noël Pouchet, and Jason Cong. Automatic hardware pragma insertion in high-level synthesis: A non-linear programming approach. ACM Transactions on Design Automation of Electronic Systems (TODAES), 30(2), 2025

    2025

  42. [48]

    High-level synthesis performance prediction using GNNs: benchmarking, modeling, and advancing

    Nan Wu, Hang Yang, Yuan Xie, Pan Li, and Cong Hao. High-level synthesis performance prediction using GNNs: benchmarking, modeling, and advancing. In Proceedings of the 59th ACM/IEEE Design Automation Conference (DAC), page 49–54, 2022

    2022

  43. [49]

    LLM4EDA: Emerging progress in large language models for electronic design automation

    Ruizhe Zhong, Xingbo Du, Shixiong Kai, Zhentao Tang, Siyuan Xu, Hui-Ling Zhen, Jianye Hao, Qiang Xu, Mingxuan Yuan, and Junchi Yan. LLM4EDA: Emerging progress in large language models for electronic design automation. arXiv preprint arXiv:2401.12224, 2023

    2023 arXiv

  44. [50]

    Betterv: controlled verilog generation with discriminative guidance

    Zehua Pei, Hui-Ling Zhen, Mingxuan Yuan, Yu Huang, and Bei Yu. Betterv: controlled verilog generation with discriminative guidance. In Proceedings of the 41st International Conference on Machine Learning (ICML), 2024

    2024

  45. [51]

    Location is key: Leveraging large language model for functional bug localization in verilog

    Bingkun Yao, Ning Wang, Jie Zhou, Xi Wang, Hong Gao, Zhe Jiang, and Nan Guan. Location is key: Leveraging large language model for functional bug localization in verilog. arXiv preprint arXiv:2409.15186, 2024

    2024 arXiv

  46. [52]

    UVLLM: An automated universal RTL verification framework using LLMs.arXiv preprint arXiv:2411.16238, 2024

    Yuchen Hu, Junhao Ye, Ke Xu, Jialin Sun, Shiyue Zhang, Xinyao Jiao, Dingrong Pan, Jie Zhou, Ning Wang, Weiwei Shan, Xinwei Fang, Xi Wang, Nan Guan, and Zhe Jiang. UVLLM: An automated universal RTL verification framework using LLMs.arXiv preprint arXiv:2411.16238, 2024

    2024 arXiv

  47. [53]

    VGV: Verilog generation using visual capabilities of multi-modal large language models

    Sam-Zaak Wong, Gwok-Waa Wan, Dongping Liu, and Xi Wang. VGV: Verilog generation using visual capabilities of multi-modal large language models. In 2024 IEEE LLM Aided Design Workshop (LAD), pages 1–5, 2024

    2024

  48. [54]

    VeriGen: A large language model for verilog code gen- eration

    Shailja Thakur, Baleegh Ahmad, Hammond Pearce, Benjamin Tan, Brendan Dolan-Gavitt, Ramesh Karri, and Siddharth Garg. VeriGen: A large language model for verilog code gen- eration. ACM Transactions on Design Automation of Electronic Systems (TODAES) , 29(3), 2024

    2024

  49. [55]

    ADO-LLM: Analog design bayesian optimiza- tion with in-context learning of large language models

    Yuxuan Yin, Yu Wang, Boxun Xu, and Peng Li. ADO-LLM: Analog design bayesian optimiza- tion with in-context learning of large language models. In Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2025

    2025

  50. [56]

    LEDRO: LLM-Enhanced design space reduction and optimization for analog circuits

    Dimple Vijay Kochar, Hanrui Wang, Anantha Chandrakasan, and Xin Zhang. LEDRO: LLM-Enhanced design space reduction and optimization for analog circuits. arXiv preprint arXiv:2411.12930, 2024

    2024 arXiv

  51. [57]

    VeriDebug: A unified LLM for verilog debugging via contrastive embedding and guided correction

    Ning Wang, Bingkun Yao, Jie Zhou, Yuchen Hu, Xi Wang, Nan Guan, and Zhe Jiang. VeriDebug: A unified LLM for verilog debugging via contrastive embedding and guided correction. arXiv preprint arXiv:2504.19099, 2025

    2025 arXiv

  52. [58]

    Insights from verification: Training a verilog generation LLM with reinforcement learning with testbench feedback

    Ning Wang, Bingkun Yao, Jie Zhou, Yuchen Hu, Xi Wang, Nan Guan, and Zhe Jiang. Insights from verification: Training a verilog generation LLM with reinforcement learning with testbench feedback. arXiv preprint arXiv:2504.15804, 2025

    2025 arXiv

  53. [59]

    Automated C/C++ program repair for high-level synthesis via large language models

    Kangwei Xu, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, and Bing Li. Automated C/C++ program repair for high-level synthesis via large language models. In Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD (MLCAD), 2024

    2024

  54. [60]

    HLSPilot: LLM-based high-level synthesis

    Chenwei Xiong, Cheng Liu, Huawei Li, and Xiaowei Li. HLSPilot: LLM-based high-level synthesis. In Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2025. 13

    2025

  55. [61]

    Optimizing high-level synthesis designs with retrieval-augmented large language models

    Haocheng Xu, Haotian Hu, and Sitao Huang. Optimizing high-level synthesis designs with retrieval-augmented large language models. In 2024 IEEE LLM Aided Design Workshop (LAD), pages 1–5, 2024

    2024

  56. [62]

    LIFT: Llm-based pragma insertion for HLS via GNN supervised fine-tuning

    Neha Prakriya, Zijian Ding, Yizhou Sun, and Jason Cong. LIFT: Llm-based pragma insertion for HLS via GNN supervised fine-tuning. arXiv preprint arXiv:2504.21187, 2025

    2025 arXiv

  57. [64]

    C2HLSC: Leveraging large language models to bridge the software-to-hardware design gap

    Luca Collini, Siddharth Garg, and Ramesh Karri. C2HLSC: Leveraging large language models to bridge the software-to-hardware design gap. arXiv preprint arXiv:2412.00214, 2024

    2024 arXiv

  58. [65]

    Can reasoning models reason about hardware? an agentic HLS perspective

    Luca Collini, Andrew Hennessee, Ramesh Karri, and Siddharth Garg. Can reasoning models reason about hardware? an agentic HLS perspective. arXiv preprint arXiv:2503.12721, 2025

    2025 arXiv

  59. [66]

    Pareto multi-task learning

    Xi Lin, Hui-Ling Zhen, Zhenhua Li, Qing-Fu Zhang, and Sam Kwong. Pareto multi-task learning. In Advances in Neural Information Processing Systems, volume 32, 2019

    2019

  60. [67]

    Profiling pareto front with multi-objective stein variational gradient descent

    Xingchao Liu, Xin Tong, and Qiang Liu. Profiling pareto front with multi-objective stein variational gradient descent. In Advances in Neural Information Processing Systems, volume 34, pages 14721–14733, 2021

    2021

  61. [68]

    MOEA/D: A multiobjective evolutionary algorithm based on decomposition

    Qingfu Zhang and Hui Li. MOEA/D: A multiobjective evolutionary algorithm based on decomposition. IEEE Transactions on Evolutionary Computation, 11(6):712–731, 2007

    2007

  62. [69]

    Learning the pareto front with hypernetworks

    Aviv Navon, Aviv Shamsian, Ethan Fetaya, and Gal Chechik. Learning the pareto front with hypernetworks. In International Conference on Learning Representations (ICLR), 2021

    2021

  63. [70]

    Pareto set learning for expensive multi-objective optimization

    Xi Lin, Zhiyuan Yang, Xiaoyuan Zhang, and Qingfu Zhang. Pareto set learning for expensive multi-objective optimization. In Proceedings of the 36th International Conference on Neural Information Processing Systems, 2022

    2022

  64. [71]

    Hypervolume maximization: a geometric view of pareto set learning

    Xiaoyuan Zhang, Xi Lin, Bo Xue, Yifan Chen, and Qingfu Zhang. Hypervolume maximization: a geometric view of pareto set learning. In Proceedings of the 37th International Conference on Neural Information Processing Systems, 2023

    2023

  65. [72]

    Panacea: Pareto alignment via preference adaptation for LLMs

    Yifan Zhong, Chengdong Ma, Xiaoyuan Zhang, Ziran Yang, Haojun Chen, Qingfu Zhang, Siyuan Qi, and Yaodong Yang. Panacea: Pareto alignment via preference adaptation for LLMs. In Advances in Neural Information Processing Systems, volume 37, pages 75522–75558, 2024

    2024

  66. [73]

    Parrot: Pareto-optimal multi-reward reinforcement learning framework for text-to-image generation

    Seung Hyun Lee, Yinxiao Li, Junjie Ke, Innfarn Yoo, Han Zhang, Jiahui Yu, Qifei Wang, Fei Deng, Glenn Entis, Junfeng He, Gang Li, Sangpil Kim, Irfan Essa, and Feng Yang. Parrot: Pareto-optimal multi-reward reinforcement learning framework for text-to-image generation. In Europ...

    2024

  67. [74]

    Evolution of heuristics: towards efficient automatic algorithm design using large language model

    Fei Liu, Xialiang Tong, Mingxuan Yuan, Xi Lin, Fu Luo, Zhenkun Wang, Zhichao Lu, and Qingfu Zhang. Evolution of heuristics: towards efficient automatic algorithm design using large language model. In Proceedings of the 41st International Conference on Machine Learning (ICML), 2024

    2024

  68. [75]

    Mathematical discoveries from program search with large language models

    Bernardino Romera-Paredes, Mohammadamin Barekatain, Alexander Novikov, Matej Balog, M Pawan Kumar, Emilien Dupont, Francisco JR Ruiz, Jordan S Ellenberg, Pengming Wang, Omar Fawzi, et al. Mathematical discoveries from program search with large language models. Nature, 625(7995...

    2024

  69. [76]

    Monte carlo tree search for compre- hensive exploration in llm-based automatic heuristic design

    Zhi Zheng, Zhuoliang Xie, Zhenkun Wang, and Bryan Hooi. Monte carlo tree search for compre- hensive exploration in llm-based automatic heuristic design. arXiv preprint arXiv:2501.08603, 2025

    2025 arXiv

  70. [77]

    Multi-objective evolution of heuristic using large language model

    Shunyu Yao, Fei Liu, Xi Lin, Zhichao Lu, Zhenkun Wang, and Qingfu Zhang. Multi-objective evolution of heuristic using large language model. In Proceedings of the AAAI Conference on Artificial Intelligence, volume 39, pages 27144–27152, 2025. 14

    2025

  71. [78]

    Reevo: Large language models as hyper-heuristics with reflective evolution

    Haoran Ye, Jiarui Wang, Zhiguang Cao, Federico Berto, Chuanbo Hua, Haeyeon Kim, Jinkyoo Park, and Guojie Song. Reevo: Large language models as hyper-heuristics with reflective evolution. arXiv preprint arXiv:2402.01145, 2024

    2024 arXiv

  72. [79]

    EvoPrompting: Language models for code-level neural architecture search

    Angelica Chen, David Dohan, and David So. EvoPrompting: Language models for code-level neural architecture search. In Advances in Neural Information Processing Systems, volume 36, pages 7787–7817, 2023

    2023

  73. [80]

    GPT-NAS: Neural architecture search meets generative pre-trained transformer model

    Caiyang Yu, Xianggen Liu, Yifan Wang, Yun Liu, Wentao Feng, Xiong Deng, Chenwei Tang, and Jiancheng Lv. GPT-NAS: Neural architecture search meets generative pre-trained transformer model. Big Data Mining and Analytics, 8(1):45–64, 2025

    2025

  74. [81]

    LLMatic: neural architecture search via large language models and quality diversity optimization

    Muhammad Umair Nasir, Sam Earle, Julian Togelius, Steven James, and Christopher Cleghorn. LLMatic: neural architecture search via large language models and quality diversity optimization. In proceedings of the Genetic and Evolutionary Computation Conference, pages 1110–1118, 2024

    2024

  75. [82]

    Graph neural architecture search with gpt-4

    Haishuai Wang, Yang Gao, Xin Zheng, Peng Zhang, Hongyang Chen, Jiajun Bu, and Philip S Yu. Graph neural architecture search with gpt-4. arXiv preprint arXiv:2310.01436, 2023

    2023

  76. [83]

    LLM guided evolution-the automation of models advancing models

    Clint Morris, Michael Jurado, and Jason Zutty. LLM guided evolution-the automation of models advancing models. In Proceedings of the Genetic and Evolutionary Computation Conference, pages 377–384, 2024

    2024

  77. [84]

    Design principle transfer in neural architecture search via large language models

    Xun Zhou, Xingyu Wu, Liang Feng, Zhichao Lu, and Kay Chen Tan. Design principle transfer in neural architecture search via large language models. In Proceedings of the AAAI Conference on Artificial Intelligence, volume 39, pages 23000–23008, 2025

    2025

  78. [86]

    High-level synthesis design space exploration: Past, present, and future

    Benjamin Carrion Schafer and Zi Wang. High-level synthesis design space exploration: Past, present, and future. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(10):2628–2639, 2020

    2020

  79. [87]

    Carloni, and Laura Pozzi

    Lorenzo Ferretti, Jihye Kwon, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, and Laura Pozzi. Leveraging prior knowledge for effective design-space exploration in high-level synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 3...

    2020

  80. [88]

    CollectiveHLS: A collaborative approach to high-level synthesis design optimization

    Aggelos Ferikoglou, Andreas Kakolyris, Dimosthenis Masouros, Dimitrios Soudris, and Sotirios Xydis. CollectiveHLS: A collaborative approach to high-level synthesis design optimization. ACM Transactions on Reconfigurable Technology and Systems, 18(1), 2024

    2024

  81. [89]

    K. Deb, A. Pratap, S. Agarwal, and T. Meyarivan. A fast and elitist multiobjective genetic algorithm: NSGA-II. IEEE Transactions on Evolutionary Computation, 6(2):182–197, 2002

    2002

  82. [90]

    PolyBench/C 4.2, 2016

    Louis-Noel Pouchet and Tomofumi Yuki. PolyBench/C 4.2, 2016. Available at: http:// polybench.sf.net

    2016

  83. [91]

    CHStone: A benchmark program suite for practical C-based high-level synthesis

    Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, and Katsuya Ishii. CHStone: A benchmark program suite for practical C-based high-level synthesis. In2008 IEEE International Symposium on Circuits and Systems (ISCAS), pages 1192–1195, 2008

    2008

  84. [92]

    Mach- suite: Benchmarks for accelerator design and customized architectures

    Brandon Reagen, Robert Adolf, Yakun Sophia Shao, Gu-Yeon Wei, and David Brooks. Mach- suite: Benchmarks for accelerator design and customized architectures. In 2014 IEEE Interna- tional Symposium on Workload Characterization (IISWC), pages 110–119. IEEE, 2014

    2014

  85. [93]

    Vitis High-Level Synthesis User Guide (UG1399), 2022

    Vitis. Vitis High-Level Synthesis User Guide (UG1399), 2022. Available at: https://docs. amd.com/r/2022.1-English/ug1399-vitis-hls

    2022

  86. [94]

    off", "on

    Marco Dorigo, Mauro Birattari, and Thomas Stutzle. Ant colony optimization. IEEE Computa- tional Intelligence Magazine, 1(4):28–39, 2006. 15 Appendix Contents A iDSE Implementation 17 A.1 Directive Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17...

    2006

  87. [95]

    – URL: https://github.com/hzkuang/HGBO-DSE • Lattice [21] – License: Available online

    Code • HGBO-DSE [31] – License: MIT license. – URL: https://github.com/hzkuang/HGBO-DSE • Lattice [21] – License: Available online. – URL: http://www.inf.usi.ch/phd/ferretti/lattice-traversing-DSE.html

  88. [96]

    – URL: http://polybench.sf.net

    Dataset • PolyBench [90] – License: Ohio State University Software Distribution License. – URL: http://polybench.sf.net. • CHStone [91] – License: Available online. – URL: https://github.com/ferrandi/CHStone • MachSuite [92] – License: MachSuite BSD-3 license. – URL: https://g...

Pith tools

Reviewed August 7, 2026 · model on record in the stance chip above.