Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links, observed 2026-08-07T04:52:57.712752Z
Paper Citation Record · LEDGER
As of 20 August 2026, this Paper Citation Record lists 23 of 23 outbound references and 1 inbound Pith citation observation for arXiv:2506.13983.
A citation records a reference. It does not transfer a finding from one paper to another.
Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links, observed 2026-08-07T04:52:57.712752Z
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-20T06:33:59.587034+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links, observed 2026-05-08T08:19:42.493657Z
A source-named dated measurement, never combined with another source.
Source: arxiv_reference, observed 2026-05-11T20:41:11.936700Z
23 of 23 outbound references displayed
External citation measurements
No source-named external measurement is stored.
Observation ce441583-6141-4dbe-9ab1-1c4486ef0478 · outbound
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine (Security) Assertions by Large Language Models
Reference 1
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation b9071a4d-b049-42fe-b3eb-29ddeaf9d143 · outbound
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine Chiraag: Chatgpt informed rapid and automated assertion generation,
Reference 2
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.
Observation 77577d9b-7591-4308-91fb-f3e3c930d38f · outbound
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine Assertllm: Generating and evaluating hardware verification assertions from design specifications via multi-llms,
Reference 4
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 6d078b8e-5c07-4baa-9042-a68f70ee2813 · outbound
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine Global Large Language Model (LLM) Research Re- port 2024-2030,
Reference 5
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.
Observation 54150c34-5968-4937-8c3e-1da2ca504a86 · outbound
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine HLSPilot: LLM-based High-Level Synthesis
Reference 6
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 59542042-1985-43dd-9604-ea3eec6a8ef5 · outbound
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine Lhs: Llm assisted efficient high-level synthesis of deep learning tasks,
Reference 7
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.
Observation 51162e04-6414-402a-84e9-1e7226e0f0f9 · outbound
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine Large language model (llm) for standard cell layout design optimization,
Reference 8
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.
Observation 68271aab-22e7-469f-80ed-f362bd926c11 · outbound
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine Automatically improving llm-based verilog generation using eda tool feedback,
Reference 9
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.
Observation 4fa89efe-2162-4925-86ef-0c4dc7bd4f20 · outbound
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine Vhdl-eval: A framework for evaluating large language models in vhdl code generation,
Reference 10
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.
Observation 31c089ac-14d0-4cd9-b5f0-84b7a6b562e7 · outbound
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine Layoutcopilot: An llm-powered multi-agent collaborative framework for interactive analog layout design,
Reference 11
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.
Observation 98236062-81e9-428b-88b9-e00c09568a03 · outbound
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine Assertllm: Generating hardware verification assertions from design specifications via multi-llms,
Reference 12
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.
Observation 51033cee-27e0-4886-853b-9053c48dd691 · outbound
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine (security) assertions by large language models,
Reference 13
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.
Observation 05db9ea7-4a4f-445a-a1d8-d8b05f097bee · outbound
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine A survey of monte carlo tree search methods,
Reference 14
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 09eabde7-cfde-42d2-ae9c-2ad25a992f67 · outbound
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine Accessing GPT-4 level Mathematical Olympiad Solutions via Monte Carlo Tree Self-refine with LLaMa-3 8B
Reference 15
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation d74b9f8c-62b4-439c-a77b-d87c812b9306 · outbound
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine Improve Mathematical Reasoning in Language Models by Automated Process Supervision
Reference 16
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 4ae882a5-8e08-47e1-b47e-874f811024c9 · outbound
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine Interpretable Contrastive Monte Carlo Tree Search Reasoning
Reference 17
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 87ef17b4-d171-4b0c-ab1a-20fed0e5b303 · outbound
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine OpenAI o1 System Card
Reference 18
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 32e1f071-e775-47e7-a347-42c0170c4e96 · outbound
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine JasperGold,
Reference 19
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.
Observation 16945369-f932-42e5-aaf6-10a6debb436e · outbound
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine Dasgupta,A Roadmap for Formal Property Verification
Reference 20
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.
Observation 485d6166-81a4-4446-abdf-6cb2a4f6adc6 · outbound
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine Unresolved cited work
Reference 21
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.
Observation dacdfe94-c6e1-4a63-a6c3-e86403f75f63 · outbound
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine Vijayaraghavan and M
Reference 22
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.
Observation 4598133f-bb9e-4cca-81a6-0b06d84292ec · outbound
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine Assertllm dataset: Generating hardware ver- ification assertions from design specifications via multi-llms,
Reference 23
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.
Observation a05812bf-c086-4443-9b2e-1b74d73e3c92 · outbound
SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine • Be very strict, ensureCORRECTNESS,CONSISTENCY, andCOMPLETENESSof the SV As
Reference 100
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.
Observation d29a0d0f-92b0-42fb-9a9c-8e46e0e34b70 · inbound
From Language to Logic: Bridging LLMs & Formal Representations for RTL Assertion Generation SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine
Reference 28
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.