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A single chip 1.024 Tb/s silicon photonics PAM4 receiver

T0 review · 2 major / 5 minor · reviewed 2026-08-06 · deepseek-v4-flash

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Pith's one-line read A monolithic 32-channel WDM PAM4 receiver chip achieves 1.024 Tb/s over one fiber at under 0.38 pJ/bit.

desk verdict The 1.024 Tb/s aggregate claim collapses under the paper's own 4-to-1 multiplexed decoder architecture, but the integrated 32-channel O-DeMux and per-channel measurements are real and worth reviewing. read the letter →

arxiv 2507.12452 v1 pith:UJNPCGBJ submitted 2025-07-16 physics.optics cs.SYeess.SY

Ali Pirmoradi , Han Hao , Kaisarbek Omirzakhov , Alexander J. Geers , Firooz Aflatouni This is my paper · ORCID
classification physics.opticscs.SYeess.SY
keywords siliconphotonicsWDMreceiverPAM4opticalinterconnectsmonolithicintegrationcapacitivephaseshifterwavelengthlockingenergyefficiency
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper reports a single-chip optical receiver that demultiplexes 32 wavelength channels from one input fiber and decodes each as a four-level PAM4 signal at 32 Gb/s, for an aggregate rate of 1.024 Tb/s. It further reports a bit-error rate below $10^{-12}$ with no equalization, pre-distortion, or digital signal processing, an end-to-end latency under 100 ps, and a chip energy efficiency under 0.38 pJ/bit. The result matters for data-center and AI interconnects, where power per bit and packaging complexity are the main constraints; a receiver that reaches terabit-scale throughput on a single fiber and locks its wavelengths at near-zero static power targets both. The paper also reports a bandwidth density above 3.55 Tb/s/mm$^2$, which it identifies as the largest reported data rate for a WDM PAM4 receiver chip to date.

What carries the argument

The central mechanism is the 1:32 optical demultiplexer: a 1:8 MZI binary tree followed by an 8:32 drop-ring resonator array, with a capacitive phase shifter and sense-actuation-memory (SAM) control loop on each tunable stage. The MZI tree is what makes the dense 200 GHz grid manageable; it first groups carriers so each ring sees only carriers spaced 1600 GHz apart, relaxing the ring isolation requirement. The capacitive phase shifters, built from the CMOS gate stack, shift resonances without DC current, and the SAM loops lock each MZI and ring to its assigned carrier using only a small tapped monitor photocurrent. That tuning machinery is what allows the zero-equalization, zero-DSP receiver to hold its $10^{-12}$ error rate despite fabrication spread and temperature drift.

What would settle it

Drive all 32 PAM4-modulated carriers into the chip simultaneously and count errors on all decoder outputs together over a sustained run; if the aggregate error rate exceeds one in $10^{12}$ bits while all 32 channels are active, the reported 1.024 Tb/s error-free claim is not a simultaneous one. A simpler check is to capture four TIA outputs through the 4-to-1 multiplexer at once, rather than one channel at a time, to confirm concurrent decoding.

Watch

Extended reading notes

Core claim

The paper's central claim is that monolithic integration of the optics and electronics, rather than a faster serial electrical front end, is the route to terabit-scale single-fiber reception. The chip separates 32 carriers spaced 200 GHz apart using a 1:8 Mach-Zehnder interferometer binary tree followed by eight branches of three drop-ring resonators; the tree first widens the channel spacing to 1600 GHz to ease ring crosstalk. Each demultiplexed channel is detected by a differential silicon-germanium photodiode pair and transimpedance amplifier, then decoded by a 2-bit time-interleaved flash PAM4 decoder. Capacitive phase shifters in the MZI and ring stages give autonomous wavelength locking at zero static power, so the receiver needs no equalization or DSP. The measured outcome is a bit-error rate below $10^{-12}$ on all 32 channels at 32 Gb/s per channel, i.e. 1.024 Tb/s on one fiber, at 0.38 pJ/bit and above 3.55 Tb/s/mm$^2$.

Load-bearing premise

The headline data rate assumes the 32 channels can be decoded at the same time, but the on-chip error measurements were taken eight channels at a time through shared decoder hardware.

Editorial extensions

If this is right

  • A single fiber can deliver 1.024 Tb/s into a receiver with no DSP or equalizer, cutting both optical-module power and packaging cost relative to multi-fiber or DSP-heavy designs.
  • At under 0.38 pJ/bit the receiver is reported as more than five times more energy efficient than existing end-to-end CMOS PAM4 receivers above 100 Gb/s, a direct benefit for power-constrained AI and data-center racks.
  • Autonomous near-zero-power wavelength locking lets the chip track thermal and process drift without spending milliwatts on heater tuning, so the energy-efficiency advantage persists in deployed conditions.
  • The >3.55 Tb/s/mm$^2$ bandwidth density suggests the receiver could sit close to a compute die in co-packaged optics without dominating package area.
  • All 32 channels meet BER below $10^{-12}$ at 32 Gb/s with a >0.05 UI timing opening, giving integration margin for a real link rather than a single-channel demo.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The same MZI-tree-plus-drop-ring architecture should extend to 64 or 128 wavelengths by adding tree stages and ring branches, since each locking loop is power-neutral and the electrical channels are replicated.
  • Scaling per-channel line rates beyond 32 Gb/s would eventually force equalization or DSP as TIA bandwidth and PAM4 eye closure become limiting; the design's margin at 32 Gb/s does not reveal where that boundary sits.
  • A full end-to-end link test with a multi-wavelength comb or laser-array transmitter would exercise realistic inter-channel crosstalk and source line noise that single-carrier receiver tests do not capture.
  • The near-zero-power capacitive tuning scheme is portable to other wavelength-selective photonic circuits, such as optical switches or sensors, wherever drift correction must cost almost no static power.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

2 major / 5 minor

Summary. The paper reports a monolithically integrated 32-channel WDM silicon-photonics PAM4 receiver in the GlobalFoundries 45CLO process. The receiver combines a 1:32 optical demultiplexer (an MZI binary tree followed by cascaded ring resonators) with capacitive and thermal phase shifters for autonomous wavelength locking, and a CMOS electrical detection chain of photodiodes, TIAs, PAM4 decoders, deserializers, and on-chip BER testers. The authors claim an aggregate data rate of 1.024 Tb/s (32 channels x 32 Gb/s) on a single input fiber, BER below 10^-12, end-to-end latency under 100 ps, energy efficiency under 0.38 pJ/bit, and a bandwidth density of 3.55 Tb/s/mm^2, all without equalization or DSP. The central experimental evidence is per-channel BER and bathtub measurements taken from a single-channel test chip and from the 32-channel chip one selected channel at a time.

Significance. If fully supported, the demonstrated receiver would be a significant advance in monolithic WDM optical receivers, combining dense wavelength-division multiplexing, near-zero-power capacitive wavelength tuning, and DSP-free PAM4 detection at record aggregate bandwidth. The paper includes useful engineering strengths: a full 32-channel monolithic demonstration, measured ring-resonator process-variation statistics, autonomous locking with low tuning power, and on-chip BER measurement. However, the headline aggregate-rate claim is not supported by the architecture as described, because the PAM4 decoders are shared through 4-to-1 multiplexers and only eight channels can be decoded simultaneously. The significance of the work therefore hinges on a load-bearing claim that the manuscript itself contradicts.

major comments (2)
  1. [Results, 'PAM4 detection and decoding' (Fig. 4a)] The text states that 'the outputs of the TIAs are 4-to-1 multiplexed and routed to PAM4 decoders followed by de-serializer and BER measurement system blocks enabling on-chip measurements of all channels, eight at a time.' This means at most eight of the 32 channels can be decoded simultaneously: one channel per 4-to-1 multiplexed group. Consequently, the demonstrated simultaneous data rate is at most 8 x 32 Gb/s = 256 Gb/s, not 1.024 Tb/s. The per-channel BER results in Fig. 5n were collected sequentially in groups of eight, not as a 32-lane concurrent link. The abstract's phrase 'concurrent electrical detection system' does not resolve this, because detection without simultaneous PAM4 decoding cannot deliver the claimed aggregate output. The headline claim of operation at 1.024 Tb/s therefore needs either evidence that all 32 channels have dedicated concurrent decoders, or a revision of the aggregate-rate claim.
  2. [Discussion and Methods (energy efficiency; bandwidth density)] The energy-efficiency calculation of about 0.38 pJ/bit uses 6.89 mW per TIA and 4.88 mW per PAM4 decoder summed over 32 channels and divided by 1.024 Tb/s. This implicitly assumes 32 decoders operating simultaneously at 32 Gb/s each. With the described 4-to-1 multiplexed decoder architecture, only eight decoders are active at once, so the efficiency at the claimed aggregate rate is not established. The bandwidth-density claim of 3.55 Tb/s/mm^2 also cannot be reproduced from the stated chip footprint (4.2 mm^2 in the introduction versus 4.72 mm^2 in Fig. 5b) and appears to depend on an unspecified area definition. Both metrics are load-bearing for the record comparisons in Fig. 1c-d and Extended Data Table 1.
minor comments (5)
  1. [Results, Fig. 5n and on-chip BER] The paper reports BER below 10^-12 for all channels but does not state the number of bits examined or the confidence interval for each BER measurement; please add this information so the BER claim is verifiable.
  2. [Abstract and Results] The 'end-to-end latency of under 100 ps' claim is not supported by any described measurement or simulation in the manuscript; either provide the measurement setup and result or remove the claim.
  3. [Introduction and Fig. 5b] The chip footprint is given as 4.2 mm^2 in the introduction and 4.72 mm^2 in the Fig. 5b caption; please reconcile these numbers and define the area used for bandwidth-density calculations.
  4. [Results, 'System integration'] In the sentence about Fig. 5j, 'WDM OAM4 receiver' appears to be a typo for 'WDM PAM4 receiver'; please correct it.
  5. [Discussion] There are minor typographical errors such as 'stat-of-the-art' and 'the stat-of-the-art' in the Discussion; please proofread the text.

Circularity Check

0 steps flagged · score 0.0 of 10

No circular derivation: the receiver demonstration rests on measured chip data, with the 4-to-1 multiplexed decoding caveat being an architectural validity question rather than a circular step.

full rationale

The paper is an experimental demonstration, not a derivation in which an output is assumed among the inputs. The headline quantities are measured on fabricated chips: per-channel BER below 10^-12 at 32 Gb/s PAM4 (Fig. 5n), per-channel TIA power of 6.89 mW, per-channel decoder power of 4.88 mW, O-DeMux insertion loss of 4 dB, and O-DeMux tuning energy of 8 fJ/bit. The aggregate data-rate is the arithmetic product of 32 channels at 32 Gb/s, and the 0.38 pJ/bit figure is measured per-channel power divided by that aggregate rate; neither reduces to its own conclusion. The self-citations [38,39] for capacitive phase shifters and autonomous wavelength locking are not load-bearing because this paper independently reports the capacitive tuning response (Fig. 3a, 3e), the locking process (Fig. 3c, 3g), and the drop-port transfer function (Fig. 3h), so the present claims do not rest solely on prior work by the same authors. No uniqueness theorem or modeling ansatz is imported from the authors' earlier papers, and the record comparison is an external survey against other groups' published chips. The one passage worth flagging is the statement in Results ('PAM4 detection and decoding', Fig. 4a) that the 4-to-1 multiplexed decoders enable 'on-chip measurements of all channels, eight at a time.' This is a potential limitation on the demonstrated simultaneity of the 32-channel aggregate rate, but it is an architectural and measurement-validity concern, not a circular reduction: the 1.024 Tb/s claim is not true by construction of any fitted parameter or self-citation. The derivation chain is therefore self-contained against measured data and external benchmarks, and no circularity is present.

Assumptions & free parameters 4 free parameters · 4 assumptions · 0 invented entities

The central claims rest on measured device performance and on assumptions about process variation and concurrent operation. The aggregate data-rate claim additionally assumes all 32 channels can be decoded simultaneously, which the architecture description does not support. No new physical entities are introduced.

free parameters (4)
  • Ring resonator coupling coefficient (k2) = 0.3
    Chosen from simulation to balance drop-port insertion loss (below 2 dB) and crosstalk (below -10 dB); it is a design choice, not fitted to the headline result.
  • Ring resonator FSR = 709-711 GHz (simulated optimum near 710 GHz)
    Selected from Extended Data Fig. 1a simulation to minimize crosstalk for carriers spaced at 1600 GHz.
  • MZI delay imbalances = 180 um, 95 um, 47.5 um
    Set to produce FSRs of 400, 800, and 1600 GHz for the binary tree demultiplexer; standard design parameters.
  • Thermal phase shifter P_pi = ~10 mW
    Measured value used in the demultiplexer power estimate; not a fitted parameter in a predictive model.
assumptions (4)
  • domain assumption GF 45CLO platform device parameters (PD responsivity ~0.9 A/W, waveguide loss ~1.4 dB/cm, grating coupler loss ~5 dB) are as stated.
    Used in the link budget and OMA calculation; if the parameters differ, sensitivity and power claims shift.
  • domain assumption The 150-ring process-variation sample on a 1.4 x 0.9 mm2 area is representative of the full 32-channel chip, and the MZI variation inferred from it is used to conclude capacitive tuning suffices.
    This supports the near-zero static power claim; larger or different variation would require thermal tuning, increasing power.
  • domain assumption Capacitive tuning ranges (0.72 nm for rings, ~0.5 FSR for MZIs) are sufficient for alignment and locking across temperature and fabrication variation.
    The near-zero power and autonomous locking claims depend on this sufficiency.
  • domain assumption PRBS7 with the on-chip BER measurement is adequate to establish BER below 1e-12.
    PRBS7 is a short test pattern; longer or more stressful patterns could yield higher BER.

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Cite this review

Pith. "Pith review of A single chip 1.024 Tb/s silicon photonics PAM4 receiver." pith.science (2026). https://pith.science/paper/UJNPCGBJ

@misc{pith2026250712452,
  author       = {Pith},
  title        = {Pith review of: A single chip 1.024 Tb/s silicon photonics PAM4 receiver},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/UJNPCGBJ}},
  note         = {Machine review of arXiv:2507.12452}
}
read the original abstract

Energy-efficient high-bandwidth interconnects play a key role in computing systems. Advances in silicon photonic electro-optic modulators and wavelength selective components have enabled the utilization of wavelength-division-multiplexing (WDM) in integrated optical transceivers, offering a high data-rate operation while achieving enhanced energy efficiency, bandwidth density, scalability, and the reach required for data-centers. Here, we report the demonstration of a single chip optical WDM PAM4 receiver, where by co-integration of a 32-channel optical demultiplexer (O-DeMux) with autonomous wavelength tuning and locking at a near-zero power consumption and a 32-channel ultra-low power concurrent electrical detection system, a record chip energy efficiency of under 0.38 pJ/bit is measured. The implemented 32 channel monolithic WDM optical receiver chip achieves an end-to-end latency of under 100 ps and a bit-error-rate of less than 10-12 with no equalization, pre-distortion, or digital-signal-processing, while operating at 1.024 Tb/s aggregate data-rate on a single input fiber, the largest reported data-rate for a WDM PAM4 receiver chip to date. The receiver bandwidth density of more than 3.55 Tb/s/mm2 corresponds to more than an order-of-magnitude larger bandwidth density-energy efficiency product compared to the state-of-the-art optical PAM4 receivers for beyond 100Gb/s links. The chip, integrated using GlobalFoundries 45CLO CMOS-photonic process, can be used for implementation of energy-efficient high data-rate optical links for AI applications.

Figures

Figures reproduced from arXiv: 2507.12452 by the authors.

Figure 3
Figure 3. (h) shows the transfer function of the drop port of a single [PITH_FULL_IMAGE:figures/full_fig_p010_3.png] view at source ↗

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