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REVIEW 3 major objections 5 minor 49 references

Arbitrary Precision Printed Ternary Neural Networks with Holistic Evolutionary Approximation

T0 review · 3 major / 5 minor · reviewed 2026-08-05 · deepseek-v4-flash

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Pith's one-line read Approximate ternary neural networks cut printed-classifier area 17x and power 59x.

desk verdict Solid engineering contribution with real novelty in approximating LTGs and co-designing ADC precision, but the headline gains are simulation-only and the reported ratios shift between abstract and body. read the letter →

arxiv 2508.19660 v3 pith:WLS4WNYZ submitted 2025-08-27 eess.SP cs.AIcs.NE

Vojtech Mrazek , Konstantinos Balaskas , Paula Carolina Lozano Duarte , Zdenek Vasicek , Mehdi B. Tahoori , Georgios Zervakis This is my paper · ORCID
classification eess.SPcs.AIcs.NE
keywords printedelectronicsternaryneuralnetworksapproximatecomputinglinearthresholdgatesevolutionarycircuitdesignADCco-designEGFETsensorclassification
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper sets out to show that printed neural-network classifiers, despite the large, slow, low-density transistors of printed electronics, can be made small and low-power enough to run on a printed battery. The route is to approximate the whole classification chain—how many bits the analog-to-digital converter delivers, how each hidden neuron decides its sign, and how output neurons count their inputs—rather than approximating only isolated arithmetic blocks. On eight sensor datasets the resulting ternary networks are reported to reach on average 17x lower area and 59x lower power than existing approximate printed neural networks, with at most 5% accuracy loss, and to be the first designs to meet a 30 mW printed-battery power budget once ADC costs are included. If the simulation-based numbers hold, flexible and disposable sensor devices could classify data on-chip instead of sending it elsewhere.

What carries the argument

The load-bearing objects are approximate linear threshold gates (LTGs) and approximate popcount circuits, both generated by Cartesian Genetic Programming. An LTG is the hidden neuron's whole decision function: sum the weighted inputs and output the sign. Approximating it as one Boolean circuit, with a distance-based error metric for sign outputs and BDD-based exact error evaluation, is what unlocks the reported area savings. Approximate popcounts replace the output-layer summations, and NSGA-II selects which approximate unit goes to which neuron. Wrapping around these, a co-design loop chooses the input precision and ADC architecture (Flash versus SAR) so that interfacing cost is included in

What would settle it

Fabricate any one of the reported approximate TNNs (for example, the 1-bit WhiteWine design, reported at 0.06 cm2 and 0.02 mW) in the same EGFET process and measure its area and power at 0.6 V; if the measured power exceeds the printed battery's 30 mW budget, or the area is much larger than reported, the central feasibility claim fails. A cheaper proxy would be comparing the EGFET standard-cell library's delay and leakage against measured printed ring oscillators.

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Extended reading notes

Core claim

The paper's central claim is that a ternary neural network tailored to a printed process can be aggressively approximated at every level without sacrificing classification. Its distinctive move is to approximate each hidden neuron as a single linear threshold gate—treating the whole 'compute weighted sum, then take the sign' operation as one circuit to be evolved—rather than approximating adders and multipliers separately. A specially designed distance error metric measures how far a wrong output is from the decision boundary, and binary decision diagrams make that error calculation exact and fast enough for evolutionary search. A second evolutionary stage then chooses, neuron by neuron, fro

Load-bearing premise

The reported area and power numbers are simulation estimates from a printed-transistor process model; no fabricated measurements are included, so the absolute savings and the 30 mW battery budget rest on that model being realistic.

Editorial extensions

If this is right

  • Across all eight datasets and both the 2% and 5% accuracy-loss thresholds, the framework reports an area-efficient solution, whereas prior approximate printed MLPs fail at least one threshold on Pendigits, Seeds, and Vertebral.
  • Including ADC costs changes the design choice: for half the networks in the comparison, the ADC is over 47% of total area, so picking the smallest sufficient input precision matters as much as approximating the classifier.
  • The reported designs are the only ones in the comparison meeting the 30 mW power budget of an existing printed battery, enabling battery-powered on-sensor inference.
  • Because the classifier is purely digital and fully combinational, the authors report that 10% analog process variation shifts accuracy by an average standard deviation of only 0.8%, with worst-case drops around 7%.
  • A surrogate area model with 0.995 Pearson correlation lets the search evaluate tens of thousands of candidate TNN designs without costly synthesis.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Beyond the paper, the single-function LTG approximation suggests a recipe for any threshold-logic classifier: approximate the decision boundary directly, not the arithmetic that feeds it. The distance error metric is a candidate surrogate for other boundary-based circuits such as comparators or binarized networks.
  • The reported quantitative claims inherit the accuracy of the EGFET process model; a fabrication study would be the natural way to confirm the printed-battery budget in real devices.
  • The authors note that very wide LTGs (over 200 input bits, as in Arrhythmia) cannot be approximated end-to-end in reasonable time; a hierarchical composition of approximate adders and comparators is the natural extension, at some optimality cost.
  • A testable next step would be applying the same co-design loop to other frontends—for example, stochastic or analog feature extractors—where ADC precision and classifier approximation interact similarly.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper proposes an automated, evolutionary framework for designing arbitrary-input-precision ternary neural networks (TNNs) in printed EGFET technology. It co-optimizes the analog-to-digital interface (Flash or SAR ADC, or ABC) and the digital classifier, approximating hidden-layer linear threshold gates (LTGs) and output-layer popcount units via Cartesian genetic programming under BDD-based error metrics, and integrating these approximate components with NSGA-II. The framework is evaluated on eight UCI datasets, with area/power estimated through Synopsys Design Compiler, PrimeTime, and the EGFET PDK in Cadence Virtuoso. The authors report large improvements over prior approximate printed MLPs/TNNs (e.g., 21x area and 67x power for 2% accuracy loss, 36x and 139x for 5% loss), claim that only their designs meet a 30 mW printed-battery power budget across all datasets at up to 5% accuracy loss, and provide Monte Carlo results on ADC process variation.

Significance. If the reported gains hold, this is a significant contribution to printed machine-learning hardware: it is, to my knowledge, the first end-to-end co-design of the analog front end and classifier for printed TNNs, and it provides an open-source framework. The paper also ships a validated area estimator (R^2 = 0.969 across 500 synthesized TNNs), BDD-based exact error analysis, a careful treatment of ADC costs, and a process-variation Monte Carlo study. The architectural ideas—approximating the entire LTG as a single function and jointly selecting input precision and approximation level—are sensible and likely to influence future printed-ML design. The main caveats are that all hardware numbers are simulation-based on an unvalidated PDK and that the headline improvement ratios are not stated consistently across abstract and body.

major comments (3)
  1. [Abstract / Section I / Section V-C] The headline claim is inconsistent. The Abstract and Section I state '17x lower area' and '59x lower power on average,' but Section V-C reports '21x lower area and 67x lower power' for the 2% loss threshold, and '36x and 139x' for the 5% threshold. Table II does not define which rows are averaged. Please explain exactly how the abstract numbers are obtained (which rows, which threshold, arithmetic vs. geometric mean). This is load-bearing because the improvement ratios are the paper's central quantitative claim.
  2. [Section III-A / Section V] All area and power numbers, including the 30 mW battery-operation claim, come from simulation with the EGFET PDK [9] and Synopsys/Cadence flows. No fabricated EGFET circuits or measured device data are presented, and the PDK's accuracy for interconnect, leakage, and minimum-area constraints in large-feature printed processes is not assessed. Since printed technologies are known to have high parasitics and variability, the absolute figures (e.g., 0.06 cm^2, 0.02 mW) could shift materially. Please add a sensitivity analysis or a comparison against measured printed-device data, and rephrase the battery-operation claim as conditioned on the PDK being representative.
  3. [Section V-B / Table II] The claim that the framework 'consistently delivers area-efficient solutions across all datasets and accuracy thresholds' is contradicted by the Arrhythmia case: Section V-B explains that 2-bit LTG approximation was not possible for inputs exceeding 200 bits, and Table II therefore reports only 1-bit Arrhythmia results. The 2-bit exact TNN has no accuracy loss while the 1-bit exact TNN loses 2%, so the 2% loss threshold is not covered for this dataset. This limitation is acknowledged in the text, but the broader 'across all datasets and accuracy thresholds' wording should be qualified.
minor comments (5)
  1. [Global] There are small typographical issues, e.g., 'V ojtech Mrazek' in the author header. Also, the introduction says 'Pendigits is the most complex dataset explored by the current state of the art' without a clear comparison baseline; please make the sentence more precise.
  2. [Section IV-C] The area estimator is validated against the same synthesis flow used for the actual results. This is fine as an internal sanity check, but the paper should state explicitly that the 0.995 correlation does not validate the underlying PDK.
  3. [Section V-B / Fig. 9] The legend in Fig. 9 is dense and the abbreviations 'epmde', 'ep', 'mde', and 'wcde' are not all defined in the caption. Adding a one-line explanation of each metric would improve readability.
  4. [Section V-C] The claim that confidence margins 'are always maintained above 1' is not supported by a figure or a table and would benefit from a definition of 'confidence margin' and a quantitative summary.
  5. [Table I / Table II] Units are inconsistent: Table I reports ADC area in mm^2, while Table II reports TNN area in cm^2. Please unify units or state conversions in the captions to avoid reader confusion.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: the LTG/popcount approximation flow and NSGA-II TNN-level search are independent of the reported results; headline area/power claims are empirical synthesis evaluations, not fitted constants or definitional identities.

full rationale

The paper's central claims (approximate LTG units, approximate popcount units, arbitrary-precision TNN co-design, and 17x/59x improvements) are supported by an implemented design flow: CGP evolves approximate circuits under explicit error thresholds, BDD-based error analysis evaluates them, NSGA-II selects approximations for each neuron, and the final area/power numbers in Table II come from Synopsys Design Compiler/PrimeTime with the EGFET PDK rather than from a closed-form identity. The surrogate area model is separately validated against 500 synthesized designs (R2 = 0.969), and key Pareto points are post-synthesis, so no 'prediction' reduces to a fitted parameter. Comparisons with [20] and with [16]-[19] are external benchmark comparisons, even though several cited baselines come from the same research groups; the paper does not rely on a self-citation as a uniqueness argument, and no ansatz is smuggled in via citation. The discrepancy between the abstract's 17x/59x and the body's 21x/67x or 36x/139x, as well as the unvalidated EGFET PDK assumptions, are correctness/robustness concerns rather than circularity. Therefore no circular step is present.

Assumptions & free parameters 3 free parameters · 4 assumptions · 0 invented entities

The central claims are empirical engineering results, so the ledger lists the tuning parameters (tau, hidden layer size, learning rate) and the external modeling assumptions (PDK accuracy, leakage dominance, error metric transferability, ADC choice) on which the reported area/power gains rest.

free parameters (3)
  • CGP error threshold tau for LTG and popcount approximation = empirically set, exact values not listed
    Controls the area-error Pareto library of approximate units (Section IV-A, V-A1). The choice of tau directly determines the available approximation strength and hence the final area/accuracy trade-off.
  • Hidden layer size per dataset and input precision = e.g., Pendigits 3b: 43; WhiteWine 3b: 12 (Table II)
    Selected via grid search in [1,50] to best match the exact MLP accuracy (Section V, Experimental Setup).
  • Training learning rate = selected from 0.001 to 0.01 via Bayesian optimization
    Used for TNN training with Adam; affects baseline accuracy (Section V).
assumptions (4)
  • domain assumption The EGFET PDK and standard cell library provide accurate area/power estimates for printed electronics
    All reported areas/powers come from Synopsys DC and PrimeTime with the EGFET library [9] (Sections III-A, V). No fabricated measurements are presented.
  • domain assumption Leakage power dominates, so minimizing area also minimizes power
    Stated in Section IV-C1: 'In printed electronics, leakage power dominates power consumption. Hence, minimizing area minimizes power as well.' This justifies optimizing area only.
  • domain assumption The LTG distance error epsilon_mde correlates with classification accuracy across all datasets, precisions, and network sizes
    The correlation is demonstrated only on Pendigits and RedWine (Fig 10); the framework assumes it holds for the other six datasets (Section V-B).
  • domain assumption Flash ADC is the optimal and only viable interface for all evaluated precisions
    Only Flash and SAR are evaluated in Table I; Binary and Sigma-Delta are dismissed as non-functional in EGFET. The claim that 'Flash outperforms SAR' is assumed to hold for all target systems (Section III-A).

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Cite this review

Pith. "Pith review of Arbitrary Precision Printed Ternary Neural Networks with Holistic Evolutionary Approximation." pith.science (2026). https://pith.science/paper/WLS4WNYZ

@misc{pith2026250819660,
  author       = {Pith},
  title        = {Pith review of: Arbitrary Precision Printed Ternary Neural Networks with Holistic Evolutionary Approximation},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/WLS4WNYZ}},
  note         = {Machine review of arXiv:2508.19660}
}
read the original abstract

Printed electronics offer a promising alternative for applications beyond silicon-based systems, requiring properties like flexibility, stretchability, conformality, and ultra-low fabrication costs. Despite the large feature sizes in printed electronics, printed neural networks have attracted attention for meeting target application requirements, though realizing complex circuits remains challenging. This work bridges the gap between classification accuracy and area efficiency in printed neural networks, covering the entire processing-near-sensor system design and co-optimization from the analog-to-digital interface-a major area and power bottleneck-to the digital classifier. We propose an automated framework for designing printed Ternary Neural Networks with arbitrary input precision, utilizing multi-objective optimization and holistic approximation. Our circuits outperform existing approximate printed neural networks by 17x in area and 59x in power on average, being the first to enable printed-battery-powered operation with under 5% accuracy loss while accounting for analog-to-digital interfacing costs.

Figures

Figures reproduced from arXiv: 2508.19660 by the authors.

Figure 1
Figure 1. Overview of a printed classification-based system. a) b) Vdd c) Vin Vref N-bit parallel counter Vin ... cmp #1 cmp #2N-2 cmp #2N-1 Vref Digital output ... ... cmp Sample& Hold Vin N-bit DAC Vref N-bit register SAR Logic log(N)-bit counter N N Digital output N [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. a) Comparator in EGFET, b) N-bit Flash ADC and c) N-bit SAR ADC. EGFET is a resistor-nMOS only technology. works, Armeniakos et al. [17] incorporated hardware-friendly weight approximation into the training process and imple￾mented post-training addition approximation using simple truncation. Afentaki et al. [18], [19] constrained weights to powers of 2—leveraging that, in bespoke circuits, a multipli￾cation by a po… view at source ↗
Figure 3
Figure 3. Bespoke exact TNN circuit overview. the output neuron with the highest value. Ternary weights {−1, 0, 1} are used in both the hidden and output layers. An abstract overview of our exact bespoke TNN circuits is illustrated in [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figures from the paper (7 more)
Figure 4
Figure 4. Figure 4: Overview of the proposed two-phase TNN approximation framework, [PITH_FULL_IMAGE:figures/full_fig_p004_4.png]
Figure 5
Figure 5. Figure 5: Miter circuit for calculating distance error [PITH_FULL_IMAGE:figures/full_fig_p006_5.png]
Figure 6
Figure 6. Figure 6: Comparison between the proposed approximation approach and the [PITH_FULL_IMAGE:figures/full_fig_p007_6.png]
Figure 8
Figure 8. Figure 8: Inverted hypervolume (i.e., AUC from [0, 0] point) for 2-bit LTGs realizing the hidden neurons of our Pendigits TNN. Both implementations from [PITH_FULL_IMAGE:figures/full_fig_p008_8.png]
Figure 10
Figure 10. Figure 10: Correlation analysis between our distance error metric (εmde) and classification accuracy for (a) Pendigits and (b) RedWine TNNs, when approximate LTGs of the same εmde error are used for their hidden neurons. networks, or from lower (1-bit) to higher (4-bit) input pr…
Figure 11
Figure 11. Figure 11: Accuracy-area analysis of approximate TNNs generated by our [PITH_FULL_IMAGE:figures/full_fig_p009_11.png]
Figure 12
Figure 12. Figure 12: Classification accuracy of our TNNs in Table II under [PITH_FULL_IMAGE:figures/full_fig_p010_12.png]

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Pith tools

Reviewed August 5, 2026 · model on record in the stance chip above.