Paper Citation Record · LEDGER

Large Language Models (LLMs) for Electronic Design Automation (EDA)

As of 18 August 2026, this Paper Citation Record lists 46 of 46 outbound references and 3 inbound Pith citation observations for arXiv:2508.20030.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2508.20030 v1

Coverage vector

measured 46 of 46 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-05T15:17:26.738977Z

measured 49 of 49 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-18T06:34:40.430872+00:00

measured 3 of 3 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-05-10T10:34:03.353104Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-05-12T10:01:29.103486Z

Reference resolution

46 of 46 outbound references displayed

verified exact0
verified fuzzy39
unresolved7
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation e8fe83bf-3eb5-4de7-9d62-06227034e378 · outbound

This paper cites Machine Learning in Advanced IC Design: A Methodological Survey,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) Machine Learning in Advanced IC Design: A Methodological Survey,

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.507356Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 1848e6a9-dfe8-4ec4-aa43-457cc378d63c · outbound

This paper cites Chip-Chat: Chal- lenges and Opportunities in Conversational Hardware Design,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) Chip-Chat: Chal- lenges and Opportunities in Conversational Hardware Design,

Reference 2

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.491849Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation d4445a67-ee2a-41a6-96e8-5e6efdbf4929 · outbound

This paper cites Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Design,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Design,

Reference 3

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.476637Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 2c886117-4070-4b0a-9cfa-53827812f1c3 · outbound

This paper cites Benchmarking Large Language Models for Automated Verilog RTL Code Generation,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) Benchmarking Large Language Models for Automated Verilog RTL Code Generation,

Reference 4

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.462068Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation f8b08a33-32ab-4051-95a7-41e529a6603a · outbound

This paper cites Large Language Models for Verification, Testing, and Design,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) Large Language Models for Verification, Testing, and Design,

Reference 5

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.447016Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation db8c42d3-45c7-490f-8ad5-cf0c8f555ad0 · outbound

This paper cites LLM-Aided Efficient Hardware Design Automation.

Large Language Models (LLMs) for Electronic Design Automation (EDA) LLM-Aided Efficient Hardware Design Automation

Reference 6

Resolution: unresolved; no resolver link, observed 2026-08-05T15:17:26.433569Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 59cc461e-139d-4582-a677-eb7db571b308 · outbound

This paper cites SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model.

Large Language Models (LLMs) for Electronic Design Automation (EDA) SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model

Reference 7

Resolution: unresolved; no resolver link, observed 2026-08-05T15:17:26.438693Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 2b195d48-a7b4-4bca-92be-81470df74bf1 · outbound

This paper cites Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback,

Reference 8

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.433018Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 5566a2f8-2ba0-427d-ab6b-64fbf1129e1e · outbound

This paper cites GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models,

Reference 9

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.417856Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 197eb328-ffd5-4b71-8920-16d863232994 · outbound

This paper cites Evaluating LLMs for Hardware Design and Test,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) Evaluating LLMs for Hardware Design and Test,

Reference 10

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.403087Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation e1ded366-1d33-4ff3-a18a-a2ebf109f7aa · outbound

This paper cites Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA,

Reference 11

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.389063Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 5b0da748-671e-4b30-b3be-31e20e985e2e · outbound

This paper cites FPGA HLS Today: Successes, Challenges, and Opportunities,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) FPGA HLS Today: Successes, Challenges, and Opportunities,

Reference 12

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.374256Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 21cedfed-5a4b-47a5-a221-aee043d2ee64 · outbound

This paper cites New solutions on LLM acceleration, optimization, and application,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) New solutions on LLM acceleration, optimization, and application,

Reference 13

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.359115Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 305f778f-b4ef-4f83-8fe2-7b839f6ff09f · outbound

This paper cites VRank: Enhancing Verilog Code Generation from Large Lan- guage Models via Self-Consistency,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) VRank: Enhancing Verilog Code Generation from Large Lan- guage Models via Self-Consistency,

Reference 14

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.344731Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 26c90166-46b4-4138-98e4-fdcb498b82eb · outbound

This paper cites VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning,

Reference 15

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.328717Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation e505c0ee-6cec-4b82-8693-d88db663b769 · outbound

This paper cites RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models.

Large Language Models (LLMs) for Electronic Design Automation (EDA) RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models

Reference 16

Resolution: unresolved; no resolver link, observed 2026-08-05T15:17:26.480901Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 243a7da4-b2bc-44a2-820a-4ef371a6f542 · outbound

This paper cites C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap,

Reference 17

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.312653Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 0bed9af1-b5e4-4777-96c6-a819ca385c15 · outbound

This paper cites AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design,

Reference 18

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.295784Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 23d91cde-3c06-43c4-9652-0cc71c75b439 · outbound

This paper cites CorrectBench: Automatic Testbench Generation with Functional Self- correction Using LLMs for HDL Design,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) CorrectBench: Automatic Testbench Generation with Functional Self- correction Using LLMs for HDL Design,

Reference 19

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.278290Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation fd249cee-20f9-42d1-b9ed-ab45197dc072 · outbound

This paper cites AssertLLM: Generating Hardware Verification Assertions from Design Speci- fications via Multi-LLMs,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) AssertLLM: Generating Hardware Verification Assertions from Design Speci- fications via Multi-LLMs,

Reference 20

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.262090Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 8a93b953-1687-4bc9-b001-ba1b376e761b · outbound

This paper cites LLSM: LLM-enhanced Logic Synthesis Model with EDA-guided CoT Prompting,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) LLSM: LLM-enhanced Logic Synthesis Model with EDA-guided CoT Prompting,

Reference 22

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.244586Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation a593338a-4518-4f66-96ef-62f9f47d3da3 · outbound

This paper cites Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesis.

Large Language Models (LLMs) for Electronic Design Automation (EDA) Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesis

Reference 23

Resolution: unresolved; no resolver link, observed 2026-08-05T15:17:26.624466Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 622b5ae1-10a0-4a8b-84c6-ebddea190250 · outbound

This paper cites VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi- Role LLMs,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi- Role LLMs,

Reference 24

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.225568Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 845a783f-10c2-42d6-8e14-7da68ed15ad7 · outbound

This paper cites Using LLMs to Facilitate Formal Verification of RTL.

Large Language Models (LLMs) for Electronic Design Automation (EDA) Using LLMs to Facilitate Formal Verification of RTL

Reference 25

Resolution: unresolved; no resolver link, observed 2026-08-05T15:17:26.633827Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 9f8d5cad-9880-4dd3-b71f-cd36b55053f1 · outbound

This paper cites LayoutCopilot: An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Design,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) LayoutCopilot: An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Design,

Reference 26

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.207240Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 1e8765c3-a4f3-4826-8e93-28063b7d37db · outbound

This paper cites HLSRewriter: Efficient Refactoring and Optimization of C/C++ Code with LLMs for High-Level Synthesis,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) HLSRewriter: Efficient Refactoring and Optimization of C/C++ Code with LLMs for High-Level Synthesis,

Reference 27

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.190946Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 54060301-5aec-4634-b91b-d7851115fedd · outbound

This paper cites Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models,

Reference 28

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.174209Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation f7992068-f325-486c-9965-43773a5d833d · outbound

This paper cites Logic Design of Neural Networks for High-Throughput and Low- Power Applications,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) Logic Design of Neural Networks for High-Throughput and Low- Power Applications,

Reference 29

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.158538Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 368fb9bd-38fb-4720-801a-eb0012c9ed2b · outbound

This paper cites HLSTester: Efficient Testing of Behavioral Discrepancies with LLMs for High-Level Synthesis,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) HLSTester: Efficient Testing of Behavioral Discrepancies with LLMs for High-Level Synthesis,

Reference 30

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.141876Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 1b037ca4-f51a-48bd-a102-faa68b28a0cd · outbound

This paper cites Fault Testing and Diagnosis Techniques for Carbon Nanotube-Based FPGAs,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) Fault Testing and Diagnosis Techniques for Carbon Nanotube-Based FPGAs,

Reference 31

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.121205Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 7b92d796-5e7c-4c2e-ae19-72fd6b209a31 · outbound

This paper cites Exploring the Mysteries of System-Level Test,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) Exploring the Mysteries of System-Level Test,

Reference 32

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.101857Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 60543627-7291-4f0a-bb5b-909e0086d026 · outbound

This paper cites Beyond structural test, the rising need for system-level test,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) Beyond structural test, the rising need for system-level test,

Reference 33

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.084366Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 274b7946-66f1-4062-915d-473a56c0a2ab · outbound

This paper cites Automating Greybox System-Level Test Generation,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) Automating Greybox System-Level Test Generation,

Reference 34

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.069137Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 53a8c6e6-5f86-4e16-9983-79d03552e6f1 · outbound

This paper cites Optimizing System-Level Test Program Generation via Genetic Programming,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) Optimizing System-Level Test Program Generation via Genetic Programming,

Reference 35

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.052371Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 436929b6-2f8c-4634-9a55-c063f456dd77 · outbound

This paper cites SonicBOOM: The 3rd Generation Berkeley Out-of-Order Machine,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) SonicBOOM: The 3rd Generation Berkeley Out-of-Order Machine,

Reference 36

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.035968Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 76851747-ad13-4fe6-b29d-818b680be469 · outbound

This paper cites Large Language Model-based Optimization for System-Level Test Program Generation,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) Large Language Model-based Optimization for System-Level Test Program Generation,

Reference 37

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.019674Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 82b761f9-5b33-4886-9cdc-177c4aee7fda · outbound

This paper cites Structured Chain-of-Thought Prompting for Code Generation.

Large Language Models (LLMs) for Electronic Design Automation (EDA) Structured Chain-of-Thought Prompting for Code Generation

Reference 38

Resolution: unresolved; no resolver link, observed 2026-08-05T15:17:26.694869Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 5b5e979e-216b-48cf-85f5-0f6f7eb0ebc2 · outbound

This paper cites DA VE: Deriving Automatically Verilog from English,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) DA VE: Deriving Automatically Verilog from English,

Reference 39

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:27.003782Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation e13a8c6b-16f0-404c-8a7e-928b7912c4ed · outbound

This paper cites VeriGen: A Large Language Model for Verilog Code Generation,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) VeriGen: A Large Language Model for Verilog Code Generation,

Reference 40

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:26.988888Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation fa5e04e6-872e-4480-b868-b1f880fd66e9 · outbound

This paper cites RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique,

Reference 41

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:26.972538Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 49ed47ef-aa8f-4a6e-b99a-2d79d91dc187 · outbound

This paper cites VerilogEval: Evaluating Large Language Models for Verilog Code Generation,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) VerilogEval: Evaluating Large Language Models for Verilog Code Generation,

Reference 42

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:26.955029Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 011bea9b-692c-4736-9de7-212f8604c569 · outbound

This paper cites CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization.

Large Language Models (LLMs) for Electronic Design Automation (EDA) CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization

Reference 43

Resolution: unresolved; no resolver link, observed 2026-08-05T15:17:26.718735Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 2d812da0-0270-4d07-a1b7-ad4afc4f1288 · outbound

This paper cites LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust,

Reference 44

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:26.939234Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 87c45272-1c82-43a2-b626-cd9b8be9e8ce · outbound

This paper cites Verileaky: Navigating IP Protection vs. Utility in Fine-Tuning for LLM- Driven Verilog Coding,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) Verileaky: Navigating IP Protection vs. Utility in Fine-Tuning for LLM- Driven Verilog Coding,

Reference 45

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:26.923363Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation a5b628d2-552b-41c1-bbe0-f4f018179217 · outbound

This paper cites RTL-Breaker: Assessing the Security of LLMs Against Backdoor Attacks on HDL Code Generation,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) RTL-Breaker: Assessing the Security of LLMs Against Backdoor Attacks on HDL Code Generation,

Reference 46

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:26.907924Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 27bb073f-8ee5-4835-a368-8c65a38a83f6 · outbound

This paper cites SALAD: Systematic Assessment of Machine Unlearning on LLM- Aided Hardware Design,.

Large Language Models (LLMs) for Electronic Design Automation (EDA) SALAD: Systematic Assessment of Machine Unlearning on LLM- Aided Hardware Design,

Reference 47

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T15:17:26.889380Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Pith citing papers

Observation 6ee89b98-2128-44f2-bf75-49254f3d57c4 · inbound

COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generation cites this paper.

COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generation Large Language Models (LLMs) for Electronic Design Automation (EDA)

Reference 38

Resolution: verified exact; arxiv_id, observed 2026-05-10T10:34:28.934689Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation d77cd7ef-91b1-4921-92eb-55d908ba70c2 · inbound

RuC: HDL-Agnostic Rule Completion Benchmark Generation cites this paper.

RuC: HDL-Agnostic Rule Completion Benchmark Generation Large Language Models (LLMs) for Electronic Design Automation (EDA)

Reference 5

Resolution: verified exact; arxiv_id, observed 2026-05-12T10:01:29.106169Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation e28b0c69-df05-4cc0-a702-dcec3f3cae0a · inbound

Complexity Horizons of Compressed Models in Analog Circuit Analysis cites this paper.

Complexity Horizons of Compressed Models in Analog Circuit Analysis Large Language Models (LLMs) for Electronic Design Automation (EDA)

Reference 1

Resolution: verified exact; arxiv_id, observed 2026-05-11T16:31:06.383281Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.