pith. sign in

arxiv: 2603.04966 · v2 · submitted 2026-03-05 · 💻 cs.ET

Programmable superconducting neuron with intrinsic in-memory computation and dual-timescale plasticity for ultra-efficient neuromorphic computing

Pith reviewed 2026-05-15 15:40 UTC · model grok-4.3

classification 💻 cs.ET
keywords superconducting neuronJosephson junctionleaky integrate-and-fireneuromorphic computingsynaptic plasticityin-memory computationspiking neural networkultra-low power
0
0 comments X

The pith

A Josephson-junction LIF neuron encodes memory and plasticity directly in its bias current for superconducting neuromorphic systems.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents a new type of superconducting neuron based on Josephson junctions that combines computation, memory, and learning in one unit. This leaky integrate-and-fire neuron uses bias currents to set its parameters, giving it built-in static memory. It shows plasticity on two timescales: fast changes in picoseconds for short-term adjustments and stable weights lasting over 10,000 seconds. The neuron runs at speeds up to 45 GHz while using only femtojoules of energy per spike and is demonstrated in a small crossbar network for spiking neural networks. If this holds, it could allow neuromorphic hardware that matches the efficiency of biological brains but at electronic speeds and superconducting low power.

Core claim

We introduce a programmable Josephson-junction-based leaky integrate-and-fire neuron featuring intrinsic static memory through bias current encoding of somatic and synaptic parameters. The device supports dual-timescale plasticity with picosecond-scale short-term spike modulation and long-term weight retention beyond 10,000 seconds. It achieves 45 GHz operation with femtojoule energy dissipation per spike, 10 threshold levels, and 20 synaptic states, and forms the basis for a crossbar spiking neural network with strong task performance.

What carries the argument

The programmable Josephson-junction-based leaky integrate-and-fire (LIF) neuron that encodes parameters in bias current to provide intrinsic memory and dual-timescale plasticity.

If this is right

  • It operates at up to 45 GHz with femtojoule-level energy per spike.
  • It supports 10 somatic threshold levels and 20 synaptic states.
  • A crossbar-based SNN using these neurons achieves strong performance on multiple tasks.
  • Short-term plasticity enables rapid adaptation while long-term retention exceeds 10,000 seconds for stable storage.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Large networks built from these neurons could eliminate the need for separate memory and compute units in AI hardware.
  • Integration with other superconducting components might create hybrid systems operating at even higher efficiencies.
  • Testing scalability would involve measuring energy and plasticity in networks with hundreds of neurons.
  • The dual-timescale feature could be applied to real-time adaptive systems like robotics or signal processing.

Load-bearing premise

Single-neuron and small-network demonstrations will translate to large-scale systems without loss of plasticity performance or rise in energy use.

What would settle it

A fabricated array of hundreds of these neurons where spike transmission plasticity fails to maintain the reported timescales or energy dissipation exceeds femtojoule levels.

read the original abstract

The escalating energy demands of artificial intelligence pose a critical challenge to conventional computing. Leveraging the efficiency of event-driven, in-memory neuromorphic architectures into the superconducting circuits with ultra-high speed and low power dissipation advantages offers a promising solution to energy-efficient computing. However, the potential of such a solution has yet to be realized, owning to the absence of a fundamental superconducting unit that unifies programmability, local memory, and multi-timescale plasticity. Here, we introduce a programmable Josephson-junction-based leaky integrate-and-fire (LIF) neuron that features intrinsic static memory and precise programmability by encoding somatic and synaptic parameters directly in the bias current. This neuron is also capable of dual-timescale plasticity: picosecond-scale short-term modulation of spike transmission and long-term weight retention exceeding 10,000 seconds, facilitating both rapid temporal adaptation and robust weight storage. It can operate up to 45 GHz with femtojoule-level energy dissipation per spike, and supports 10 somatic threshold levels and 20 synaptic states. Furthermore, we demonstrate a crossbar-based spiking neural network (SNN) utilizing this neuron, which achieves outstanding performance across multiple tasks. By fusing computation, memory and plasticity into a single superconducting unit, our work paves the way for the next generation of ultrafast, energy-efficient neuromorphic computing.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 1 minor

Summary. The paper introduces a programmable Josephson-junction-based leaky integrate-and-fire (LIF) neuron that encodes somatic and synaptic parameters directly in bias currents to provide intrinsic static memory and precise programmability. It claims dual-timescale plasticity (picosecond-scale short-term modulation and long-term retention exceeding 10,000 s), operation up to 45 GHz with femtojoule energy per spike, support for 10 somatic threshold levels and 20 synaptic states, and demonstrates a crossbar-based SNN achieving strong performance on multiple tasks.

Significance. If the single-neuron properties and small-network results hold and extend without degradation, the work would represent a notable advance in superconducting neuromorphic hardware by unifying computation, memory, and multi-timescale plasticity in one unit, potentially enabling ultra-high-speed, low-power event-driven systems that address AI energy demands.

major comments (1)
  1. [Crossbar SNN demonstration] Crossbar SNN demonstration section: the central claim of 'ultra-efficient neuromorphic computing' rests on the assumption that bias-current-encoded programmability and >10 ks retention scale to large arrays, yet no analysis is provided of bias-line crosstalk, on-chip current-source uniformity across thousands of lines, or thermal-noise effects on long-term state retention; the reported 10-neuron/20-state small-network results therefore do not establish this load-bearing condition.
minor comments (1)
  1. [Abstract] Abstract and results sections: quantitative claims (45 GHz, fJ/spike, exact retention times, 10/20 state counts) should be accompanied by explicit experimental data, error bars, circuit diagrams, and derivation steps in the main text rather than stated without supporting figures or tables.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the positive assessment of the work's significance and for the constructive major comment. We address the point below and will revise the manuscript accordingly to strengthen the presentation of scalability considerations.

read point-by-point responses
  1. Referee: [Crossbar SNN demonstration] Crossbar SNN demonstration section: the central claim of 'ultra-efficient neuromorphic computing' rests on the assumption that bias-current-encoded programmability and >10 ks retention scale to large arrays, yet no analysis is provided of bias-line crosstalk, on-chip current-source uniformity across thousands of lines, or thermal-noise effects on long-term state retention; the reported 10-neuron/20-state small-network results therefore do not establish this load-bearing condition.

    Authors: We agree that explicit analysis of array-level effects is necessary to support claims of ultra-efficient neuromorphic computing at scale. The current manuscript focuses on validating the core programmable LIF neuron and its dual-timescale plasticity in a small 10-neuron crossbar to establish the fundamental unit. In the revised version we will add a new subsection (or expanded discussion) that includes: (i) SPICE-level simulations of bias-line crosstalk for arrays up to 100×100, (ii) estimates of on-chip current-source mismatch based on typical superconducting fabrication tolerances, and (iii) thermal-noise analysis showing that retention >10 ks remains feasible when the long-term state is stored in persistent Josephson-junction flux quanta rather than volatile bias currents. These additions will clarify that the small-network results demonstrate the building block while identifying design rules for larger implementations. We will also tone down any implication that the 10-neuron results alone prove large-array performance. revision: yes

Circularity Check

0 steps flagged

No circularity: device demonstration is self-contained

full rationale

The paper describes an experimental Josephson-junction LIF neuron whose parameters are set by bias currents and whose plasticity is measured directly. No equations, derivations, or fitted-parameter predictions appear in the provided text; the claims rest on single-neuron and small-crossbar measurements (threshold levels, retention times, energy per spike) rather than any self-referential reduction. Self-citations, if present, are not load-bearing for the core hardware result, satisfying the criterion for an independent, non-circular presentation.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Abstract-only review; no explicit free parameters, axioms, or invented entities are stated beyond standard Josephson-junction physics assumed from prior literature.

pith-pipeline@v0.9.0 · 5574 in / 1043 out tokens · 30832 ms · 2026-05-15T15:40:51.563863+00:00 · methodology

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Reference graph

Works this paper leans on

47 extracted references · 47 canonical work pages · 1 internal anchor

  1. [1]

    f, SPICE simulation waveforms of the synapse with a weight of 4

    e, Synapse circuit diagram and state machine of NDRO. f, SPICE simulation waveforms of the synapse with a weight of 4. Bias-current programmability A key requirement for scalable neuromorphic hardware is the ability to store and update computational parameters directly within the processing elements themselves. Remarkably, the superconducting neuron and s...

  2. [2]

    & Goswami, S

    S, H., Bhat, N. & Goswami, S. Neuromorphic pathways for transforming AI hardware. Nat Electron 8, 752–756 (2025). https://doi.org/10.1038/s41928-025-01432-z

  3. [3]

    Neuromorphic electronic systems

    Mead, C. Neuromorphic electronic systems. Proceedings of the IEEE 78, 1629 –1636 (1990). 12 of 20 https://doi.org/10.1109/5.58356

  4. [4]

    A., Arthur, J

    Merolla, P. A., Arthur, J. V ., Alvarez-Icaza, R., Cassidy, A. S., Sawada, J., Akopyan, F., Jackson, B. L., Imam, N., Guo, C., Nakamura, Y ., Brezzo, B., V o, I., Esser, S. K., Appuswamy, R., Taba, B., Amir, A., Flickner, M. D., Risk, W. P., Manohar, R. & Mod ha, D. S. A million spiking -neuron integrated circuit with a scalable communication network and ...

  5. [5]

    Davies, M., Srinivasa, N., Lin, T.-H., Chinya, G., Cao, Y ., Choday, S. H., Dimou, G., Joshi, P., Imam, N., Jain, S., Liao, Y ., Lin, C.-K., Lines, A., Liu, R., Mathaikutty, D., McCoy, S., Paul, A., Tse, J., Venkataramanan, G., Weng, Y .-H., Wild, A., Yang, Y. & Wang, H. Loihi: A Neuromorphic Manycore Processor with On-Chip Learning. IEEE Micro 38, 82–99 ...

  6. [6]

    & Shi, L

    Pei, J., Deng, L., Song, S., Zhao, M., Zhang, Y ., Wu, S., Wang, G., Zou, Z., Wu, Z., He, W., Chen, F., Deng, N., Wu, S., Wang, Y ., Wu, Y ., Yang, Z., Ma, C., Li, G., Han, W., Li, H., Wu, H., Zhao, R., Xie, Y . & Shi, L. Towards artificial general intelligence with hybrid Tianjic chip architecture. Nature 572, 106–111 (2019). https://doi.org/10.1038/s415...

  7. [7]

    1.1 Computing’s energy problem (and what we can do about it)

    Horowitz, M. 1.1 Computing’s energy problem (and what we can do about it). In 2014 IEEE International Solid -State Circuits Conference Digest of Technical Papers (ISSCC) (pp. 10–14) (2014)

  8. [8]

    & Segall, K

    Schneider, M., Toomey, E., Rowlands, G., Shainline, J., Tschirhart, P. & Segall, K. SuperMind: a survey of the potential of superconducting electronics for neuromorphic computing. Supercond. Sci. Technol. 35, 053001 (2022). https://doi.org/10.1088/1361-6668/ac4cd2

  9. [9]

    Likharev, K. K. & Semenov, V . K. RSFQ logic/memory family: a new Josephson-junction technology for sub -terahertz- clock-frequency digital systems. IEEE Transactions on Applied Superconductivity 1, 3 –28 (1991). https://doi.org/10.1109/77.80745

  10. [10]

    & Schult, D

    Segall, K., Purmessur, C., D’Addario, A. & Schult, D. A superconducting synapse exhibiting spike -timing dependent plasticity. Appl. Phys. Lett. 122, (2023). https://doi.org/10.1063/5.0150687

  11. [11]

    A., Bozbey, A

    Karamuftuoglu, M. A., Bozbey, A. & Razmkhah, S. JJ -Soma: Toward a Spiking Neuromorphic Processor Architecture. IEEE Transactions on Applied Superconductivity 33, 1–7 (2023). https://doi.org/10.1109/TASC.2023.3270766

  12. [12]

    & Toepfer, H

    Feldhoff, F. & Toepfer, H. Niobium Neuron: RSFQ Based Bio -Inspired Circuit. IEEE Transactions on Applied Superconductivity 31, 1–5 (2021). https://doi.org/10.1109/TASC.2021.3063212

  13. [13]

    & Segall, K

    Crotty, P., Schult, D. & Segall, K. Josephson junction simulation of neurons. Phys. Rev. E 82, 011914 (2010). https://doi.org/10.1103/PhysRevE.82.011914

  14. [14]

    & Toepfer, H

    Feldhoff, F. & Toepfer, H. Short- and Long-Term State Switching in the Superconducting Niobium Neuron Plasticity. IEEE Transactions on Applied Superconductivity 34, 1–5 (2024). https://doi.org/10.1109/TASC.2024.3355876

  15. [15]

    & Berggren, K

    Toomey, E., Segall, K., Castellani, M., Colangelo, M., Lynch, N. & Berggren, K. K. Superconducting Nanowire Spiking Element for Neural Networks. Nano Lett. 20, 8059–8066 (2020). https://doi.org/10.1021/acs.nanolett.0c03057

  16. [16]

    Zhang, H., Gang, C., Xu, C., Gong, G. & Lu, H. Brain-Inspired Spiking Neural Network Using Superconducting Devices. IEEE Transactions on Emerging Topics in Computational Intelligence 7, 271 –277 (2023). https://doi.org/10.1109/TETCI.2021.3089328

  17. [17]

    L., Donnelly, C

    Schneider, M. L., Donnelly, C. A., Haygood, I. W., Wynn, A., Russek, S. E., Castellanos -Beltran, M. A., Dresselhaus, P. D., Hopkins, P. F., Pufall, M. R. & Rippard, W. H. Synaptic weighting in single flux quantum neuromorphic computing. Sci Rep 10, 934 (2020). https://doi.org/10.1038/s41598-020-57892-0

  18. [18]

    S., Walker, H., Krause, K

    Cheng, R., Goteti, U. S., Walker, H., Krause, K. M., Oeding, L. & Hamilton, M. C. Toward Learning in Neuromorphic Circuits Based on Quantum Phase Slip Junctions. Front. Neurosci. 15, (2021). https://doi.org/10.3389/fnins.2021.765883

  19. [19]

    B., Semenov, V

    Golden, E. B., Semenov, V . K. & Tolpygo, S. K. Development of a Neuromorphic Network Using BioSFQ Circuits. IEEE 13 of 20 Transactions on Applied Superconductivity 35, 1–7 (2025). https://doi.org/10.1109/TASC.2025.3538699

  20. [20]

    & You, H

    Liu, Z., Chen, S., Qu, P., Liu, H., Niu, M., Ying, L., Ren, J., Tang, G. & You, H. SUSHI: Ultra-High-Speed and Ultra-Low- Power Neuromorphic Chip Using Superconducting Single -Flux-Quantum Circuits. In 56th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 614–627) (2023)

  21. [21]

    Z., Kopur, Y ., Karamuftuoglu, M

    Song, C., Caliskan, A., Ucpinar, B. Z., Kopur, Y ., Karamuftuoglu, M. A., Razmkhah, S., Nazarian, S. & Pedram, M. SuperSNN: A Hardware -Aware Framework for Physically Realizable, High -Performance Superconducting Spiking Neural Network Chips. (2025) . https://doi.org/10.48550/arXiv.2509.05532

  22. [22]

    & You, L

    Jiang, H., Wang, Z., Huang, J., Chen, G., Zhang, Z., Ye, X., Fan, D. & You, L. JSNPE: A Digital Superconducting Spiking Neural Processing Element. IEEE Transactions on Applied Superconductivity 35, 1 –12 (2025). https://doi.org/10.1109/TASC.2025.3561667

  23. [23]

    & Yamashita, T

    Mizugaki, Y ., Nakajima, K., Sawada, Y . & Yamashita, T. Superconducting neural circuits using fluxon pulses. Appl. Phys. Lett. 62, 762–764 (1993). https://doi.org/10.1063/1.108571

  24. [24]

    & Wang, Z

    Ying, L., Zhang, X., Niu, M., Ren, J., Peng, W., Maezawa, M. & Wang, Z. Development of Multi-Layer Fabrication Process for SFQ Large Scale Integrated Digital Circuits. IEEE Transactions on Applied Superconductivity 31, 1 –4 (2021). https://doi.org/10.1109/TASC.2021.3065277

  25. [25]

    C., Schrader, S., Potjans, W., Schemmel, J., Diesmann, M

    Pfeil, T., Potjans, T. C., Schrader, S., Potjans, W., Schemmel, J., Diesmann, M. & Meier, K. Is a 4 -Bit Synaptic Weight Resolution Enough? – Constraints on Enabling Spike -Timing Dependent Plasticity in Neuromorphic Hardware. Front. Neurosci. 6, (2012). https://doi.org/10.3389/fnins.2012.00090

  26. [26]

    & Mayr, C

    George, R., Chiappalone, M., Giugliano, M., Levi, T., Vassanelli, S., Partzsch, J. & Mayr, C. Plasticity and Adaptation in Neuromorphic Biohybrid Systems. iScience 23, 101589 (2020). https://doi.org/10.1016/j.isci.2020.101589

  27. [27]

    & Prodromakis, T

    Berdan, R., Vasilaki, E., Khiat, A., Indiveri, G., Serb, A. & Prodromakis, T. Emulating short-term synaptic dynamics with memristive devices. Sci Rep 6, 18639 (2016). https://doi.org/10.1038/srep18639

  28. [28]

    R., Moraitis, T., Parnell, T., Tuma, T., Rajendran, B., Leblebici, Y ., Sebastian, A

    Boybat, I., Le Gallo, M., Nandakumar, S. R., Moraitis, T., Parnell, T., Tuma, T., Rajendran, B., Leblebici, Y ., Sebastian, A. & Eleftheriou, E. Neuromorphic computing with multi -memristive synapses. Nat Commun 9, 2514 (2018). https://doi.org/10.1038/s41467-018-04933-y

  29. [29]

    Huang, W., Xia, X., Zhu, C., Steichen, P., Quan, W., Mao, W., Yang, J., Chu, L. & Li, X. Memristive Artificial Synapses for Neuromorphic Computing. Nano-Micro Lett. 13, 85 (2021). https://doi.org/10.1007/s40820-021-00618-2

  30. [30]

    Life and death of colloidal bonds control the rate-dependent rheology of gels

    Choi, S., Bezugam, S. S., Bhattacharya, T., Kwon, D. & Strukov, D. B. Wafer -scale fabrication of memristive passive crossbar circuits for brain-scale neuromorphic computing. Nat Commun 16, 8757 (2025). https://doi.org/10.1038/s41467- 025-63831-2

  31. [31]

    & Wong, N

    Hong, H., Du, Z., Jiang, M., Mao, R., Ren, Y ., Li, F., Mao, W., Peng, M., Zhang, W., Liu, Z., Li, C. & Wong, N. Memristor- based adaptive analog-to-digital conversion for efficient and accurate compute-in-memory. Nat Commun 16, 9749 (2025). https://doi.org/10.1038/s41467-025-65233-w

  32. [32]

    & Prodromakis, T

    Stathopoulos, S., Michalas, L., Khiat, A., Serb, A. & Prodromakis, T. An Electrical Characterisation Methodology for Benchmarking Memristive Device Technologies. Sci Rep 9, 19412 (2019). https://doi.org/10.1038/s41598-019-55322-4

  33. [33]

    Zinoviev, D. Y . & Polyakov, Y . A. Octopux: an advanced automated setup for testing superconductor circuits. IEEE Transactions on Applied Superconductivity 7, 3240–3243 (1997). https://doi.org/10.1109/77.622039

  34. [34]

    Massey Jr., F. J. The Kolmogorov-Smirnov Test for Goodness of Fit. Journal of the American Statistical Association 46, 68–78 (1951). https://doi.org/10.1080/01621459.1951.10500769

  35. [35]

    Gradient-based learning applied to document recognition,

    Lecun, Y ., Bottou, L., Bengio, Y . & Haffner, P. Gradient-based learning applied to document recognition. Proceedings of the IEEE 86, 2278–2324 (1998). https://doi.org/10.1109/5.726791

  36. [36]

    Fashion-MNIST: a Novel Image Dataset for Benchmarking Machine Learning Algorithms

    Xiao, H., Rasul, K. & V ollgraf, R. Fashion -MNIST: a Novel Image Dataset for Benchmarking Machine Learning 14 of 20 Algorithms. (2017) . https://doi.org/10.48550/arXiv.1708.07747

  37. [37]

    Mukhanov, O. A. Energy-Efficient Single Flux Quantum Technology. IEEE Transactions on Applied Superconductivity 21, 760–769 (2011). https://doi.org/10.1109/TASC.2010.2096792

  38. [38]

    https://irds.ieee.org/editions/2023/20-roadmap-2023-edition/129-irds%E2%84%A2-2023-cryogenic-electronics-and- quantum-information-processing, (accessed on 11 November 2025)

    IRDSTM 2023: Cryogenic Electronics and Quantum Information Processing - IEEE IRDS TM. https://irds.ieee.org/editions/2023/20-roadmap-2023-edition/129-irds%E2%84%A2-2023-cryogenic-electronics-and- quantum-information-processing, (accessed on 11 November 2025)

  39. [39]

    IEEE Transactions on Comput

    Akopyan, F., Sawada, J., Cassidy, A., Alvarez-Icaza, R., Arthur, J., Merolla, P., Imam, N., Nakamura, Y ., Datta, P., Nam, G.-J., Taba, B., Beakes, M., Brezzo, B., Kuang, J. B., Manohar, R., Risk, W. P., Jackson, B. & Modha, D. S. TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip. IEEE Transactions on Computer-Aid...

  40. [40]

    B., Galluppi, F., Temple, S

    Furber, S. B., Galluppi, F., Temple, S. & Plana, L. A. The SpiNNaker Project. Proceedings of the IEEE 102, 652–665 (2014). https://doi.org/10.1109/JPROC.2014.2304638

  41. [41]

    & Di Carlo, S

    Carpegna, A., Savino, A. & Di Carlo, S. Spiker: an FPGA-optimized Hardware accelerator for Spiking Neural Networks. In 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (pp. 14–19) (2022)

  42. [42]

    & Pan, G

    Ma, D., Jin, X., Sun, S., Li, Y ., Wu, X., Hu, Y ., Yang, F., Tang, H., Zhu, X., Lin, P. & Pan, G. Darwin3: a large -scale neuromorphic chip with a novel ISA and on-chip learning. NSR 11, nwae102 (2024). https://doi.org/10.1093/nsr/nwae102

  43. [43]

    A survey on intent-based networking,

    Yang, S., Ren, J., Liu, B. & Gao, X. JSICsim —An Analog Simulator for Superconductor Integrated Circuit. IEEE Transactions on Circuits and Systems II: Express Briefs 70, 1129 –1133 (2023). https://doi.org/10.1109/TCSII.2022.3215912. MISCELLANEA Supplementary material Supplementary material associated with this article can be found in the supplementary fil...

  44. [44]

    Zhang, X. et al. Hybrid memristor -CMOS neurons for in-situ learning in fully hardware memristive spiking neural networks. Sci. Bull. 66, 1624–1633 (2021)

  45. [45]

    Shaban, A., Bezugam, S. S. & Suri, M. An adaptive threshold neuron for recurrent spiking neural networks with nanodevice hardware implementation. Nat. Commun. 12, 4234 (2021)

  46. [46]

    Tannu, S. S. et al. A case for superconducting accelerators. in Proceedings of the 16th ACM International Conference on Computing Frontiers 67–75 (Association for Computing Machinery, New York, NY , USA, 2019). doi:10.1145/3310273.3321561

  47. [47]

    Mukhanov, O. A. Energy-Efficient Single Flux Quantum Technology. IEEE Trans. Appl. Supercond. 21, 760–769 (2011)