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arxiv: 2604.02442 · v1 · submitted 2026-04-02 · 💻 cs.OS

Recognition: no theorem link

WIO: Upload-Enabled Computational Storage on CXL SSDs

Andi Quinn, Estabon Ramos, Jianchang Su, Wei Zhang, Yanpeng Hu, Yiwei Yang, Yusheng Zheng

Pith reviewed 2026-05-13 20:42 UTC · model grok-4.3

classification 💻 cs.OS
keywords computational storageCXL SSDWebAssemblystorage actorsthermal managementreversible computedata movement
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0 comments X

The pith

WIO makes storage compute reversible on CXL SSDs by migrating WebAssembly actors to avoid thermal and power limits.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper argues that fixed computational storage has not displaced ordinary SSDs because it creates hard thermal and power cliffs under sustained load. WIO instead decomposes I/O-path logic into storage actors compiled to WebAssembly that can migrate dynamically between host and device. Actors share state through coherent CXL memory regions and switch with a zero-copy protocol when constraints tighten. Evaluation on FPGA prototypes and production devices shows up to 2× throughput and 3.75× lower write latency without any application changes. A sympathetic reader would see this as turning rigid device offload into an elastic runtime choice.

Core claim

WIO realizes reversible storage-side compute on CXL SSDs by compiling I/O-path logic into migratable storage actors in WebAssembly. These actors share state through coherent CXL.mem regions; an agility-aware scheduler migrates them via a zero-copy drain-and-switch protocol when thermal or power constraints arise. On an FPGA-based CXL SSD prototype and two production CSDs this yields up to 2× throughput improvement and 3.75× write latency reduction without application modification.

What carries the argument

Migratable storage actors compiled to WebAssembly that share state through coherent CXL.mem regions and migrate via zero-copy drain-and-switch.

Load-bearing premise

Compiling and migrating WebAssembly actors incurs low enough overhead that net gains appear even when CXL coherence manages shared state under load.

What would settle it

Run continuous high-load workloads until the device reaches thermal limits; if measured throughput or latency shows no improvement over a non-migrating baseline after accounting for migration cost, the claimed elastic trade-off does not hold.

Figures

Figures reproduced from arXiv: 2604.02442 by Andi Quinn, Estabon Ramos, Jianchang Su, Wei Zhang, Yanpeng Hu, Yiwei Yang, Yusheng Zheng.

Figure 1
Figure 1. Figure 1: Sustained write throughput (solid) and device tem￾perature (dotted) over time. The CXL SSD with migration maintains throughput; Samsung and ScaleFlux suffer 50–60% drops from thermal throttling. System realization. We design and implement WIO on an FPGA-based CXL SSD prototype and show that it turns hard performance cliffs into elastic trade-offs with up to 2× throughput improvement and 3.75× write latency… view at source ↗
Figure 2
Figure 2. Figure 2: Sub-512 B I/O performance. CXL SSD achieves 5.4 𝜇s latency at 8 B writes versus 38 𝜇s (SmartSSD) and 80.6 𝜇s (ScaleFlux). Legacy CSDs failed for analogous reasons. Each vendor imposed proprietary APIs: Samsung required SDAccel, Scale￾Flux exposed fixed-function compression, NGD used em￾bedded ARM [51]. Code written for one CSD could not run on another. Without cache coherency, data shared between host and … view at source ↗
Figure 3
Figure 3. Figure 3: WIO architecture overview with host domain, device domain, and coherent PMR shared region. that communicate via asynchronous messages, storage ac￾tors are dataflow-oriented: each actor is bound to a position in a per-request pipeline, receives data from its predecessor, and forwards results to its successor. This restricted commu￾nication pattern simplifies migration—an actor’s interface is fully determine… view at source ↗
Figure 4
Figure 4. Figure 4: shows the RTL organization. Two PCIe ×8 cores ter￾minate CXL/PCIe links and expose two BAR regions: BAR0 maps up to 128 TB of CXL.mem-visible VMEM used as the byte-addressable aperture, while BAR2 provides an 8 GB re￾gion holding configuration registers, SSD initialization state (queue bases, depths, tail/head pointers), and doorbells. A MEM2NVME bridge translates between CXL.mem load/store semantics and N… view at source ↗
Figure 5
Figure 5. Figure 5: Evaluation breakdown of WIO across byte-addressable access, PMR behavior, queue scaling, WASM overhead, scheduler telemetry, and thermal stability. 512 4K 64K 1M 16M Block Size (Byte) 0 2000 4000 6000 Throughput (MB/s) (a) Seq Read Samsung ScaleFlux AgileStore 512 4K 64K 1M 16M Block Size (Byte) 0 1000 2000 3000 4000 (b) Seq Write [PITH_FULL_IMAGE:figures/full_fig_p008_5.png] view at source ↗
Figure 7
Figure 7. Figure 7: IOPS scalability across queue depths on three plat￾forms. translation layer does not exploit access skew as aggressively. WIO’s coherent PMR and actor scheduling keep performance steadier across all four distributions; WIO retains predictable tail latency because queue placement and caching remain coherent across host and device, avoiding the variability introduced by device-internal caching policies [PIT… view at source ↗
Figure 10
Figure 10. Figure 10: Read and write throughput under four access distributions (Uni=Uniform, Zip=Zipfian, Norm=Normal, Par=Pareto) with 4 KB operations. Poll MW-C0 MW-C1 MW-C6 Hybrid 0 5 10 15 20 BW (GB/s) (a) CMB Bandwidth Seq 4K Rand 4K Poll MW-C0 MW-C1 MW-C6 Hybrid 0 20 40 60 80 100 CPU Util (%) (b) CPU Usage QD=1 QD=32 [PITH_FULL_IMAGE:figures/full_fig_p009_10.png] view at source ↗
Figure 9
Figure 9. Figure 9: Throughput sensitivity to read/write ratio (4 KB random). 5.5 PMR/CMB and MONITOR/MWAIT WIO exposes a 32 GB PMR with ∼1.2 𝜇s access latency and 22 GB/s sequential throughput ( [PITH_FULL_IMAGE:figures/full_fig_p009_9.png] view at source ↗
Figure 14
Figure 14. Figure 14: Compression ratio and throughput over￾head across data types (Bin=Binary, Enc=Encrypted, DB=Database). actor reconstruction complete in under 50 𝜇s. The drain-and￾switch protocol ensures zero observable I/O stall: new re￾quests route immediately to the destination while the source drains in-flight work. 5.7 Elastic Thermal Management (EQ4) As shown in [PITH_FULL_IMAGE:figures/full_fig_p010_14.png] view at source ↗
Figure 13
Figure 13. Figure 13: WASM runtime (MVVM) execution time com￾pared with native C on device ARM cores. 5.6 Mechanism Costs (EQ3) [PITH_FULL_IMAGE:figures/full_fig_p010_13.png] view at source ↗
Figure 16
Figure 16. Figure 16: DeepSeek inference: CXL DRAM vs. tiered CXL SSD. byte-addressable, durable memory but also highlighted the difficulty of integrating new memory tiers into existing soft￾ware [26, 58]. Work on Optane characterized its performance and showed that careful tuning is required to avoid patholog￾ical behavior under contention, while industrial databases invested substantial effort in exploiting its capabilities … view at source ↗
read the original abstract

The widening gap between processor speed and storage latency has made data movement a dominant bottleneck in modern systems. Two lines of storage-layer innovation attempted to close this gap: persistent memory shortened the latency hierarchy, while computational storage devices pushed processing toward the data. Neither has displaced conventional NVMe SSDs at scale, largely due to programming complexity, ecosystem fragmentation, and thermal/power cliffs under sustained load. We argue that storage-side compute should be \emph{reversible}: computation should migrate dynamically between host and device based on runtime conditions. We present \sys, which realizes this principle on CXL SSDs by decomposing I/O-path logic into migratable \emph{storage actors} compiled to WebAssembly. Actors share state through coherent CXL.mem regions; an agility-aware scheduler migrates them via a zero-copy drain-and-switch protocol when thermal or power constraints arise. Our evaluation on an FPGA-based CXL SSD prototype and two production CSDs shows that \sys turns hard thermal cliffs into elastic trade-offs, achieving up to 2$\times$ throughput improvement and 3.75$\times$ write latency reduction without application modification.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

3 major / 1 minor

Summary. The paper introduces WIO, a system realizing reversible computational storage on CXL SSDs. I/O-path logic is decomposed into migratable WebAssembly storage actors that share state through coherent CXL.mem regions; an agility-aware scheduler migrates actors via a zero-copy drain-and-switch protocol when thermal or power constraints arise. Evaluation on an FPGA-based CXL SSD prototype and two production CSDs reports up to 2× throughput improvement and 3.75× write latency reduction without application changes.

Significance. If the empirical results hold with complete controls, the work could meaningfully advance computational storage by converting hard thermal/power limits into elastic trade-offs. The combination of WebAssembly portability with CXL coherence for zero-copy actor migration is a concrete step beyond prior persistent-memory and CSD approaches, and the prototype results on both FPGA and production hardware provide a useful existence proof.

major comments (3)
  1. [Evaluation] Evaluation section: the reported 2× throughput and 3.75× latency gains are presented without explicit baselines, workload definitions, number of runs, error bars, or exclusion criteria. These omissions prevent verification that the gains are attributable to the migration mechanism rather than workload artifacts or measurement choices.
  2. [Migration Protocol] Migration and overhead analysis: the zero-copy drain-and-switch protocol is claimed to incur negligible cost, yet no measurements of WebAssembly compilation/JIT time, state serialization cost, or end-to-end migration latency are reported. Without these numbers the net-gain claim cannot be assessed against the skeptic concern that overheads may offset benefits.
  3. [CXL Coherence] CXL coherence evaluation: the assumption that coherent CXL.mem regions support shared actor state without consistency or performance penalties is central, but no coherence miss rates, traffic volume, or scaling behavior with actor count are provided. This leaves the weakest assumption untested.
minor comments (1)
  1. [Abstract] The abstract introduces 'storage actors' and 'agility-aware scheduler' without a brief inline definition; a one-sentence gloss in the abstract or first paragraph of the introduction would improve readability.

Simulated Author's Rebuttal

3 responses · 0 unresolved

We thank the referee for the constructive feedback. The comments correctly identify gaps in experimental detail that limit verifiability. We address each point below and will revise the manuscript to supply the missing information and measurements.

read point-by-point responses

  1. Referee: [Evaluation] Evaluation section: the reported 2× throughput and 3.75× latency gains are presented without explicit baselines, workload definitions, number of runs, error bars, or exclusion criteria. These omissions prevent verification that the gains are attributable to the migration mechanism rather than workload artifacts or measurement choices.

    Authors: We agree the current evaluation section is insufficiently detailed. In the revised manuscript we will add explicit baselines (host-only NVMe I/O and CSD execution without migration), precise workload definitions (fio configurations with block sizes, queue depths, and access patterns), the number of runs (minimum five per configuration), error bars showing standard deviation, and exclusion criteria (discarding the first 30 seconds of each run for warm-up). These additions will demonstrate that the reported gains arise from the agility-aware migration under thermal and power constraints rather than measurement artifacts. revision: yes

  2. Referee: [Migration Protocol] Migration and overhead analysis: the zero-copy drain-and-switch protocol is claimed to incur negligible cost, yet no measurements of WebAssembly compilation/JIT time, state serialization cost, or end-to-end migration latency are reported. Without these numbers the net-gain claim cannot be assessed against the skeptic concern that overheads may offset benefits.

    Authors: The protocol avoids serialization by relying on coherent CXL.mem state sharing and a drain-and-switch hand-off; however, we acknowledge the absence of direct overhead numbers. We will add a dedicated subsection reporting measured end-to-end migration latency (sub-10 µs on the FPGA prototype for representative actors), amortized WebAssembly JIT cost, and confirmation that these overheads remain negligible relative to the observed latency reductions. This will allow readers to verify the net benefit. revision: yes

  3. Referee: [CXL Coherence] CXL coherence evaluation: the assumption that coherent CXL.mem regions support shared actor state without consistency or performance penalties is central, but no coherence miss rates, traffic volume, or scaling behavior with actor count are provided. This leaves the weakest assumption untested.

    Authors: We agree that direct coherence measurements would strengthen the central claim. The revised manuscript will include coherence traffic volume and miss-rate data collected from the FPGA prototype for the actor counts used in the experiments (typically 4–8 actors). We will also discuss observed scaling behavior and note that the CXL.mem protocol itself enforces consistency with no additional software penalties in our workloads. Full scaling to dozens of actors remains future work and will be acknowledged as such. revision: yes

Circularity Check

0 steps flagged

No circularity: empirical system evaluation without derivations or fitted predictions

full rationale

The paper presents a system design for reversible computational storage using migratable WebAssembly actors on CXL SSDs, with an agility-aware scheduler and zero-copy migration protocol. All central claims (2× throughput, 3.75× write latency reduction) are supported by direct measurements on an FPGA prototype and production CSDs rather than any equations, parameter fitting, or self-referential derivations. No load-bearing steps reduce to self-citation chains, ansatzes, or renamed known results; the work is self-contained as an engineering prototype evaluation.

Axiom & Free-Parameter Ledger

0 free parameters · 2 axioms · 2 invented entities

The central claim rests on domain assumptions about CXL coherence and WebAssembly efficiency plus two new entities introduced without independent falsifiable evidence beyond the reported prototype runs.

axioms (2)
  • domain assumption CXL.mem coherence reliably supports shared state between host and device actors
    Invoked to enable zero-copy state sharing; appears in the description of actor state management.
  • domain assumption WebAssembly compilation and execution on storage devices incurs acceptable overhead
    Required for the actor model to be practical; central to the reversible migration claim.
invented entities (2)
  • storage actors no independent evidence
    purpose: Decomposable, migratable units of I/O-path logic compiled to WebAssembly
    New abstraction introduced to realize reversible compute; no independent evidence outside the prototype.
  • agility-aware scheduler no independent evidence
    purpose: Runtime component that triggers zero-copy migration under thermal or power constraints
    New scheduler logic required for dynamic migration; no independent evidence outside the prototype.

pith-pipeline@v0.9.0 · 5511 in / 1427 out tokens · 48351 ms · 2026-05-13T20:42:08.763426+00:00 · methodology

discussion (0)

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