arxiv: 2604.05191 · v2 · submitted 2026-04-06 · 💻 cs.ET

Recognition: 1 theorem link

· Lean Theorem

Experimental Demonstration of an On-Chip CMOS-Integrated 3T-1MTJ Probabilistic Bit -- A P-Bit

Xuejian Zhang , John Arnesh Divakaruni Daniel , Neil Dilley , Zhihong Chen , Joerg Appenzeller

Authors on Pith no claims yet

Pith reviewed 2026-05-10 18:41 UTC · model grok-4.3

classification 💻 cs.ET

keywords probabilistic bitP-Bitstochastic magnetic tunnel junctionCMOS integrationprobabilistic computingneuromorphic computingmagnetic tunnel junction

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The pith

A circuit of three transistors and one stochastic magnetic tunnel junction produces tunable random bits integrated on a CMOS chip.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper demonstrates the first experimental realization of a probabilistic bit, or P-Bit, fully integrated into a standard CMOS process using only three transistors and one stochastic magnetic tunnel junction. This P-Bit generates stochastic voltage outputs that swing between the full supply rails and can be tuned by applied voltages. The work includes simulations showing the P-Bit operating in probabilistic logic circuits. This approach promises to bring probabilistic computing, which excels at solving problems with inherent uncertainty, into existing semiconductor manufacturing flows for better energy efficiency.

Core claim

The authors have fabricated and tested an on-chip 3T-1MTJ P-Bit that exhibits rail-to-rail stochastic output behavior, marking the first such demonstration with a stochastic MTJ in a complete CMOS integration.

What carries the argument

The 3T-1 sMTJ probabilistic bit circuit, where the stochastic magnetic tunnel junction acts as the source of tunable randomness controlled by the transistor network.

If this is right

The P-Bit can serve as a building block for probabilistic logic circuits, as verified through simulations.
Integration with CMOS allows for monolithic large-scale probabilistic computing architectures on chips.
Such devices support low-power solutions for probability-encoded computational problems.
Neuromorphic computing schemes can incorporate this P-Bit for enhanced capabilities.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

If scaled, arrays of these P-Bits could solve optimization and sampling problems more efficiently than deterministic methods in certain domains.
The successful integration suggests that similar stochastic devices could be combined with digital logic on the same die without process conflicts.
Testing in actual probabilistic algorithms beyond simulations would be a next step to validate system-level benefits.

Load-bearing premise

The stochastic switching properties of the magnetic tunnel junction are preserved through the CMOS fabrication steps and electrical environment without significant degradation.

What would settle it

If repeated measurements of the P-Bit output show deterministic rather than stochastic voltage levels or no response to tuning voltages after integration, the central claim would be invalidated.

read the original abstract

Ongoing semiconductor scaling challenges and the rise of neuromorphic computing have sparked interest in exploring novel computing schemes to achieve higher power efficiency and computational capabilities. Probabilistic computing is one candidate that endows low power consumption, capability of solving probability-encoded computational problems, and the ease of integration with existing CMOS technology. A basic building block of this scheme is the probabilistic bit (P-Bit), which utilizes a novel device such as a stochastic magnetic tunnel junction (sMTJ) to generate tunable randomness by nature. This work presents the first experimental demonstration of a fully CMOS-integrated sMTJ-based P-Bit, capable of generating rail-to-rail stochastic output with a mere collection of 3 transistors + 1 sMTJ. Furthermore, simulations also confirm this P-Bit's functionality in probabilistic logic circuits. The demonstration of such P-Bit paves the way towards realizing monolithic large-scale probabilistic computing architecture on CMOS chips.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

They built and tested the first 3T-1MTJ P-bit fully integrated on CMOS with an sMTJ, which is a practical experimental step even if the output statistics need scrutiny.

read the letter

The punchline is that this is the first reported experimental integration of a 3T-1MTJ probabilistic bit using a stochastic MTJ on a CMOS chip, producing rail-to-rail stochastic signals. They do a good job showing that the sMTJ can be monolithically integrated with CMOS transistors without losing its ability to generate tunable randomness. The use of only three transistors keeps the circuit compact, which is useful for scaling to larger probabilistic computing arrays. The simulations they include demonstrate how this P-bit could fit into basic logic circuits for probabilistic computing, which helps connect the device to system-level applications. The soft spots are around the experimental data. The abstract claims the functionality, but to really evaluate how well the stochastic behavior holds up after integration, I'd want to see the actual output statistics, any degradation from fabrication, and how the tunability works in practice. If those details are in the full paper with proper error bars and multiple devices, it strengthens the case; otherwise the claim rests more on the integration success than on quantified performance. The citation pattern looks reasonable, referencing earlier sMTJ work and probabilistic computing concepts without obvious gaps or self-referential loops. This paper is for device physicists and hardware engineers working on beyond-CMOS or neuromorphic computing. Someone building probabilistic hardware would find the integration approach useful as a starting point. I think it deserves peer review. The experimental demonstration of the integrated P-bit is a practical advance worth checking in detail by referees familiar with MTJ devices.

Referee Report

1 major / 1 minor

Summary. The paper claims the first experimental demonstration of a fully CMOS-integrated stochastic MTJ (sMTJ)-based probabilistic bit (P-Bit) realized with a 3T-1MTJ circuit that produces rail-to-rail stochastic output. Simulations are said to confirm functionality within probabilistic logic circuits, with the overall goal of enabling monolithic large-scale probabilistic computing on CMOS chips.

Significance. If the experimental results are substantiated, the work would be significant for probabilistic computing by showing that a minimal 3T-1MTJ topology can be monolithically integrated with standard CMOS while preserving tunable stochastic behavior, thereby supporting low-power, scalable hardware for probability-encoded algorithms.

major comments (1)

[Abstract] The central claim is an experimental demonstration, yet the provided manuscript text contains no measured waveforms, output statistics, error bars, device parameters, or integration-process details to verify that rail-to-rail stochastic switching was achieved post-fabrication. This directly bears on the soundness of the primary result.

minor comments (1)

[Abstract] The abstract uses the informal phrase 'a mere collection of'; a more precise formulation such as 'using only three transistors and one sMTJ' would be appropriate for a journal submission.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the constructive feedback. We address the major comment below and will strengthen the manuscript accordingly.

read point-by-point responses

Referee: [Abstract] The central claim is an experimental demonstration, yet the provided manuscript text contains no measured waveforms, output statistics, error bars, device parameters, or integration-process details to verify that rail-to-rail stochastic switching was achieved post-fabrication. This directly bears on the soundness of the primary result.

Authors: We agree that the manuscript text would benefit from more explicit descriptions of the experimental results. The full manuscript contains measured data from the fabricated 3T-1MTJ circuit, including waveforms demonstrating rail-to-rail stochastic output and supporting statistics. In the revised version we will add detailed textual descriptions of these measured waveforms, output statistics with error bars, extracted device parameters, and the CMOS integration process details to better substantiate the experimental claims. revision: yes

Circularity Check

0 steps flagged

No significant circularity in experimental demonstration

full rationale

The paper is an experimental demonstration of a 3T-1MTJ P-Bit after CMOS integration, with the central claim resting on fabrication, integration, and measurement of stochastic output rather than any derivation chain, first-principles prediction, or fitted model. No equations, ansatzes, or predictions are presented that could reduce to inputs by construction; the abstract and provided text reference simulations only in passing without load-bearing self-citations or uniqueness theorems. The result is therefore self-contained as an empirical finding with no circular steps.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The demonstration rests on the domain assumption that sMTJs retain stochastic behavior after CMOS integration; no free parameters or new entities are introduced in the abstract.

axioms (1)

domain assumption Stochastic magnetic tunnel junctions generate tunable randomness suitable for P-bits
Invoked in the abstract as the basis for the P-bit functionality

pith-pipeline@v0.9.0 · 5480 in / 1130 out tokens · 26649 ms · 2026-05-10T18:41:49.826423+00:00 · methodology

discussion (0)

Lean theorems connected to this paper

Citations machine-checked in the Pith Canon. Every link opens the source theorem in the public Lean library.

IndisputableMonolith/Foundation/RealityFromDistinction.lean reality_from_one_distinction unclear

?

unclear
Relation between the paper passage and the cited Recognition theorem.

first experimental demonstration of a fully CMOS-integrated sMTJ-based P-Bit, capable of generating rail-to-rail stochastic output with a mere collection of 3 transistors + 1 sMTJ

What do these tags mean?

matches: The paper's claim is directly supported by a theorem in the formal canon.
supports: The theorem supports part of the paper's argument, but the paper may add assumptions or extra steps.
extends: The paper goes beyond the formal theorem; the theorem is a base layer rather than the whole result.
uses: The paper appears to rely on the theorem as machinery.
contradicts: The paper's claim conflicts with a theorem or certificate in the canon.
unclear: Pith found a possible connection, but the passage is too broad, indirect, or ambiguous to say the theorem truly supports the claim.

Reference graph

Works this paper leans on

52 extracted references

[1]

Inexact computing using probabilistic circuits: Ultra low-power digital processing,

J. Kim and S. Tiwari, “Inexact computing using probabilistic circuits: Ultra low-power digital processing, ” ACM J. Emerg. Technol. Comput. Syst., vol. 10, no. 2, pp. 1–23, Feb. 2014

2014
[2]

Probabilistic deep spiking neural systems enabled by magnetic tunnel junction,

A. Sengupta, M. Parsa, B. Han, and K. Roy, “Probabilistic deep spiking neural systems enabled by magnetic tunnel junction, ” IEEE Trans. Electron Devices, vol. 63, no. 7, pp. 2963–2970, July 2016

2016
[3]

Stochastic-based synapse and soft-limiting neuron with spintronic devices for low power and robust artificial neural networks,

Y . Bai, D. Fan, and M. Lin, “Stochastic-based synapse and soft-limiting neuron with spintronic devices for low power and robust artificial neural networks, ” IEEE Trans. Multi-scale Comput. Syst., vol. 4, no. 3, pp. 463–476, July 2018

2018
[4]

Implementing Bayesian networks with embedded stochastic MRAM,

R. Faria, K. Y . Camsari, and S. Datta, “Implementing Bayesian networks with embedded stochastic MRAM, ” AIP Adv., vol. 8, no. 4, p. 45101, Apr. 2018

2018
[5]

Survey of stochastic-based computation paradigms,

M. Alawad and M. Lin, “Survey of stochastic-based computation paradigms, ” IEEE Trans. Emerg. Top. Comput., vol. 7, no. 1, pp. 98–114, Jan. 2019

2019
[6]

Weighted p -bits for FPGA implementation of probabilistic circuits,

A. Z. Pervaiz, B. M. Sutton, L. A. Ghantasala, and K. Y . Camsari, “Weighted p -bits for FPGA implementation of probabilistic circuits, ” IEEE Trans. Neural Netw. Learn. Syst., vol. 30, no. 6, pp. 1920– 1926, June 2019

1920
[7]

Autonomous probabilistic coprocessing with petaflips per second,

B. Sutton, R. Faria, L. A. Ghantasala, R. Jaiswal, K. Y . Camsari, and S. Datta, “Autonomous probabilistic coprocessing with petaflips per second, ” IEEE Access, vol. 8, pp. 157238–157252, 2020

2020
[8]

The promise of spintronics for unconventional computing,

G. Finocchio, M. Di Ventra, K. Y . Camsari, K. Everschor-Sitte, P . Khalili Amiri, and Z. Zeng, “The promise of spintronics for unconventional computing, ” J. Magn. Magn. Mater., vol. 521, no. 167506, p. 167506, Mar. 2021

2021
[9]

Probabilistic computing with p-bits,

J. Kaiser and S. Datta, “Probabilistic computing with p-bits, ” Appl. Phys. Lett., vol. 119, no. 15, p. 150503, Oct. 2021

2021
[10]

Massively parallel probabilistic computing with sparse Ising machines,

N. A. Aadit et al., “Massively parallel probabilistic computing with sparse Ising machines, ” Nat. Electron., vol. 5, no. 7, pp. 460–468, June 2022

2022
[11]

Bayesian neural networks using magnetic tunnel junction-based probabilistic in- memory computing,

S. Liu et al., “Bayesian neural networks using magnetic tunnel junction-based probabilistic in- memory computing, ” Front. Nanotechnol., vol. 4, p. 1021943, Oct. 2022

2022
[12]

Review of magnetic tunnel junctions for stochastic computing,

B. R. Zink, Y . Lv, and J.-P . Wang, “Review of magnetic tunnel junctions for stochastic computing, ” IEEE J. Explor. Solid-state Comput. Devices Circuits, vol. 8, no. 2, pp. 173–184, Dec. 2022

2022
[13]

Unconventional computing based on magnetic tunnel junction,

B. Cai et al., “Unconventional computing based on magnetic tunnel junction, ” Appl. Phys. A Mater. Sci. Process., vol. 129, no. 4, p. 236, Apr. 2023

2023
[14]

A full-stack view of probabilistic computing with p-bits: Devices, architectures, and algorithms,

S. Chowdhury et al., “A full-stack view of probabilistic computing with p-bits: Devices, architectures, and algorithms, ” IEEE J. Explor. Solid-state Comput. Devices Circuits, vol. 9, no. 1, pp. 1–11, June 2023

2023
[15]

Probabilistic neural computing with stochastic devices,

S. Misra et al., “Probabilistic neural computing with stochastic devices, ” Adv. Mater., vol. 35, no. 37, p. e2204569, Sept. 2023

2023
[16]

An integrated-circuit-based probabilistic computer that uses voltage-controlled magnetic tunnel junctions as its entropy source,

C. Duffee et al., “An integrated-circuit-based probabilistic computer that uses voltage-controlled magnetic tunnel junctions as its entropy source, ” Nat. Electron., pp. 1–10, Aug. 2025

2025
[17]

Superparamagnetic and stochastic- write magnetic tunnel junctions for high-speed true random number generation in advanced computing,

J. Z. Sun, C. Safranski, S. Koswatta, P . Hashemi, and A. D. Kent, “Superparamagnetic and stochastic- write magnetic tunnel junctions for high-speed true random number generation in advanced computing, ” J. Phys. D Appl. Phys., vol. 59, no. 1, p. 13002, Jan. 2026

2026
[18]

Low-barrier nanomagnets as p-bits for spin logic,

R. Faria, K. Y . Camsari, and S. Datta, “Low-barrier nanomagnets as p-bits for spin logic, ” IEEE Magn. Lett., vol. 8, pp. 1–5, 2017

2017
[19]

Implementing p-bits With Embedded MTJ,

K. Y . Camsari, S. Salahuddin, and S. Datta, “Implementing p-bits With Embedded MTJ, ” IEEE Electron Device Lett., vol. 38, no. 12, pp. 1767–1770, Dec. 2017

2017
[20]

p-Transistors, p-bits and p-circuits for an invertible logic,

K. Y . Camsari, “p-Transistors, p-bits and p-circuits for an invertible logic, ” in 2017 75th Annual Device Research Conference (DRC), IEEE, June 2017, pp. 1–2

2017
[21]

P-bits for probabilistic spin logic,

K. Y . Camsari, B. M. Sutton, and S. Datta, “P-bits for probabilistic spin logic, ” Appl. Phys. Rev., vol. 6, no. 1, p. 11305, Mar. 2019

2019
[22]

From Charge to Spin and Spin to Charge: Stochastic Magnets for Probabilistic Switching,

K. Y . Camsari et al., “From Charge to Spin and Spin to Charge: Stochastic Magnets for Probabilistic Switching, ” Proc. IEEE, vol. 108, no. 8, pp. 1322–1337, Aug. 2020

2020
[23]

Training deep Boltzmann networks with sparse Ising machines,

S. Niazi, S. Chowdhury, N. A. Aadit, M. Mohseni, Y . Qin, and K. Y . Camsari, “Training deep Boltzmann networks with sparse Ising machines, ” Nat. Electron., vol. 7, no. 7, pp. 610–619, June 2024

2024
[24]

Tunable spintronic devices with different switching mechanisms for probabilistic and stochastic computing,

B. R. Zink et al., “Tunable spintronic devices with different switching mechanisms for probabilistic and stochastic computing, ” Phys. Rev. Appl., vol. 24, no. 4, p. 47001, Oct. 2025

2025
[25]

Configurable p-Neurons Using Modular p-Bits,

S. Bunaiyan et al., “Configurable p-Neurons Using Modular p-Bits, ” arXiv [cs.ET], Jan. 2026

2026
[26]

Theory of tunnel magnetoresistance and spin filter effect in magnetic tunnel junctions,

H. Itoh, “Theory of tunnel magnetoresistance and spin filter effect in magnetic tunnel junctions, ” J. Phys. D Appl. Phys., vol. 40, no. 5, p. 1228, Feb. 2007

2007
[27]

Tunneling magnetoresistance from a symmetry filtering effect,

W. H. Butler, “Tunneling magnetoresistance from a symmetry filtering effect, ” Sci. Technol. Adv. Mater., vol. 9, no. 1, p. 14106, Jan. 2008

2008
[28]

Spin transfer torques,

D. C. Ralph and M. D. Stiles, “Spin transfer torques, ” J. Magn. Magn. Mater., vol. 320, no. 7, pp. 1190– 1216, Apr. 2008

2008
[29]

Spin-transfer torque switching in magnetic tunnel junctions and spin-transfer torque random access memory,

Z. Diao et al., “Spin-transfer torque switching in magnetic tunnel junctions and spin-transfer torque random access memory, ” J. Phys. Condens. Matter, vol. 19, no. 16, p. 165209, Apr. 2007

2007
[30]

Magnetoresistive random access memory,

D. Apalkov, B. Dieny, and J. M. Slaughter, “Magnetoresistive random access memory, ” Proc. IEEE Inst. Electr. Electron. Eng., vol. 104, no. 10, pp. 1796–1830, Oct. 2016

2016
[31]

A Magnetic Tunnel Junction based True Random Number Generator with conditional perturb and real-time output probability tracking,

W. H. Choi et al., “A Magnetic Tunnel Junction based True Random Number Generator with conditional perturb and real-time output probability tracking, ” in 2014 IEEE International Electron Devices Meeting, IEEE, Dec. 2014, pp. 12.5.1–12.5.4

2014
[32]

Future prospects of MRAM technologies,

S. Yuasa et al., “Future prospects of MRAM technologies, ” in 2013 IEEE International Electron Devices Meeting, IEEE, Dec. 2013, pp. 3.1.1–3.1.4

2013
[33]

Spin dice: A scalable truly random number generator based on spintronics,

A. Fukushima et al., “Spin dice: A scalable truly random number generator based on spintronics, ” Appl. Phys. Express, vol. 7, no. 8, p. 83001, Aug. 2014

2014
[34]

Random bitstream generation using voltage-controlled magnetic anisotropy and spin orbit torque magnetic tunnel junctions,

S. Liu et al., “Random bitstream generation using voltage-controlled magnetic anisotropy and spin orbit torque magnetic tunnel junctions, ” IEEE J. Explor. Solid-state Comput. Devices Circuits, vol. 8, no. 2, pp. 194–202, Dec. 2022

2022
[35]

Measurement-driven neural-network training for integrated magnetic tunnel junction arrays,

W. A. Borders et al., “Measurement-driven neural-network training for integrated magnetic tunnel junction arrays, ” Phys. Rev. Appl., vol. 21, no. 5, p. 54028, May 2024

2024
[36]

Low-Energy Truly Random Number Generation with Superparamagnetic Tunnel Junctions for Unconventional Computing,

D. Vodenicarevic et al., “Low-Energy Truly Random Number Generation with Superparamagnetic Tunnel Junctions for Unconventional Computing, ” Phys. Rev. Appl., vol. 8, no. 5, p. 54045, Nov. 2017

2017
[37]

Integer factorization using stochastic magnetic tunnel junctions,

W. A. Borders, A. Z. Pervaiz, S. Fukami, K. Y . Camsari, H. Ohno, and S. Datta, “Integer factorization using stochastic magnetic tunnel junctions, ” Nature, vol. 573, no. 7774, pp. 390–393, Sept. 2019

2019
[38]

Probabilistic computing with binary stochastic neurons,

A. Z. Pervaiz, S. Datta, and K. Y . Camsari, “Probabilistic computing with binary stochastic neurons, ” in 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), IEEE, Nov. 2019, pp. 1–6

2019
[39]

Computing with invertible logic: Combinatorial optimization with probabilistic bits,

N. A. Aadit, A. Grimaldi, M. Carpentieri, L. Theogarajan, G. Finocchio, and K. Y . Camsari, “Computing with invertible logic: Combinatorial optimization with probabilistic bits, ” in 2021 IEEE International Electron Devices Meeting (IEDM), IEEE, Dec. 2021, pp. 40.3.1–40.3.4

2021
[40]

CMOS plus stochastic nanomagnets enabling heterogeneous computers for probabilistic inference and learning,

K. Kobayashi et al., “CMOS plus stochastic nanomagnets enabling heterogeneous computers for probabilistic inference and learning, ” Nat. Commun., vol. 15, no. 1, p. 2685, Apr. 2023

2023
[41]

Demonstration of nanosecond operation in stochastic magnetic tunnel junctions,

C. Safranski, J. Kaiser, P . Trouilloud, P . Hashemi, G. Hu, and J. Z. Sun, “Demonstration of nanosecond operation in stochastic magnetic tunnel junctions, ” Nano Lett., vol. 21, no. 5, pp. 2040–2045, Mar. 2021

2040
[42]

Nanosecond true-random-number generation with superparamagnetic tunnel junctions: Identification of joule heating and spin-transfer-torque effects,

L. Schnitzspan, M. Kläui, and G. Jakob, “Nanosecond true-random-number generation with superparamagnetic tunnel junctions: Identification of joule heating and spin-transfer-torque effects, ” Phys. Rev. Appl., vol. 20, no. 2, p. 24002, Aug. 2023

2023
[43]

Entropy-assisted nanosecond stochastic operation in perpendicular superparamagnetic tunnel junctions,

L. Soumah et al., “Entropy-assisted nanosecond stochastic operation in perpendicular superparamagnetic tunnel junctions, ” Phys. Rev. Appl., vol. 24, no. 1, p. L11002, July 2025

2025
[44]

Stochastic 𝑝-Bits for Invertible Logic

K. Y . Camsari, R. Faria, B. M. Sutton, and S. Datta, “Stochastic 𝑝-Bits for Invertible Logic” , Phys. Rev. X, vol. 7, no. 3, p. 31014, July 2017

2017
[45]

Experimental demonstration of an on-chip p-bit core based on stochastic magnetic tunnel junctions and 2D MoS2 transistors,

J. Daniel et al., “Experimental demonstration of an on-chip p-bit core based on stochastic magnetic tunnel junctions and 2D MoS2 transistors, ” Nat. Commun., vol. 15, no. 1, p. 4098, May 2024

2024
[46]

A true random number generator for probabilistic computing using stochastic magnetic actuated random transducer devices,

A. Shukla et al., “A true random number generator for probabilistic computing using stochastic magnetic actuated random transducer devices, ” in 2023 24th International Symposium on Quality Electronic Design (ISQED), IEEE, Apr. 2023, pp. 1–10

2023
[47]

Experimental demonstration of a compact spintronics-based platform with high- quality tunable random number generation for probabilistic computing,

J. Daniel et al., “Experimental demonstration of a compact spintronics-based platform with high- quality tunable random number generation for probabilistic computing, ” in Spintronics XVII, H. Jaffrès, J.- E. Wegrowe, M. Razeghi, and J. S. Friedman, Eds., SPIE, Oct. 2024, p. 93

2024
[48]

Current control of time-averaged magnetization in superparamagnetic tunnel junctions,

M. Bapna and S. A. Majetich, “Current control of time-averaged magnetization in superparamagnetic tunnel junctions, ” Appl. Phys. Lett., vol. 111, no. 24, p. 243107, Dec. 2017

2017
[49]

Design of stochastic nanomagnets for probabilistic spin logic,

P . Debashis, R. Faria, K. Y . Camsari, and Z. Chen, “Design of stochastic nanomagnets for probabilistic spin logic, ” IEEE Magn. Lett., vol. 9, pp. 1–5, 2018

2018
[50]

Nanosecond random telegraph noise in in-plane magnetic tunnel junctions,

K. Hayakawa et al., “Nanosecond random telegraph noise in in-plane magnetic tunnel junctions, ” Phys. Rev. Lett., vol. 126, no. 11, p. 117202, Mar. 2021

2021
[51]

Developing spin-transfer torque (STT)-resistant stochastic MTJs for complementary metal-oxide-semiconductor (CMOS)-integrated probabilistic bits,

J. Daniel, X. Zhang, Z. Chen, and J. Appenzeller, “Developing spin-transfer torque (STT)-resistant stochastic MTJs for complementary metal-oxide-semiconductor (CMOS)-integrated probabilistic bits, ” in Spintronics XVIII, H. Jaffrès, J.-E. Wegrowe, M. Razeghi, and J. S. Friedman, Eds., SPIE, Sept. 2025, p. 59

2025
[52]

Experimental evaluation of simulated quantum annealing with MTJ-augmented p- bits,

A. Grimaldi et al., “Experimental evaluation of simulated quantum annealing with MTJ-augmented p- bits, ” in 2022 International Electron Devices Meeting (IEDM), IEEE, Dec. 2022.[53]N. S. Singh et al., “Hardware demonstration of feedforward stochastic neural networks with fast MTJ-based p-bits, ” pp. 1– 4, Dec. 2023

2022