arxiv: 2604.06667 · v1 · submitted 2026-04-08 · 💻 cs.ET

Recognition: 2 theorem links

· Lean Theorem

Computing In Spintronic Memory: A Thermal Perspective

Patrick Miller , H\"usrev Cilasun , Sachin S. Sapatnekar , Ulya R. Karpuzcu

Authors on Pith no claims yet

Pith reviewed 2026-05-10 18:36 UTC · model grok-4.3

classification 💻 cs.ET

keywords computing-in-memoryspintronicthermal analysispower densitylateral conductionmemory arraystemperature distribution

0 comments

The pith

Spintronic computing-in-memory maintains uniform temperature that increases linearly with active cells and decreases linearly with array size.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper seeks to characterize the thermal effects of performing computation directly inside spintronic memory arrays instead of moving data to a separate processor. It establishes that lateral thermal conduction keeps the temperature nearly the same everywhere in the array. Temperature rises in proportion to the number of cells engaged in computation. It falls in proportion to the total size of the array. The particular memory technology fixes the power density and sets the thermal profile. Readers would care because this lets engineers estimate whether thermal issues will constrain the use of such efficient but active memory systems.

Core claim

Computing in spintronic memory arrays produces a mostly uniform temperature distribution thanks to lateral thermal conduction. Temperature rises linearly with the count of memory cells that participate in the computation. Temperature falls linearly with the size of the memory array. The memory technology controls the power density and therefore the thermal characteristics of the system.

What carries the argument

Lateral thermal conduction in the plane of the memory array that equalizes temperature and yields linear dependencies on the number of active cells and the array dimensions.

If this is right

No localized thermal hotspots are expected to form in these arrays.
Increasing the array size reduces the temperature rise for a fixed computational task.
The thermal behavior is primarily determined by the choice of spintronic memory variant through its power density.
Thermal analysis can use simple linear models rather than detailed simulations for initial estimates.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

The uniformity and scaling relations may allow architects to ignore spatial thermal variation when evaluating spintronic CiM designs.
If verified in silicon, the results could extend to guiding thermal budgeting in related in-memory computing approaches.
Larger arrays might become preferable for workloads with high simultaneous activity to stay within temperature limits.

Load-bearing premise

A simplified thermal model that omits detailed circuit layout, variations in material properties, and validation against real fabricated devices can still predict the temperatures that occur in spintronic memory arrays.

What would settle it

Direct temperature measurements on a physical spintronic computing-in-memory array, taken while varying the number of active cells and the array dimensions, would confirm or contradict the predicted uniform distribution and linear scaling laws.

Figures

Figures reproduced from arXiv: 2604.06667 by H\"usrev Cilasun, Patrick Miller, Sachin S. Sapatnekar, Ulya R. Karpuzcu.

**Figure 1.** Figure 1: Example row and cell layout with control lines to orchestrate memory and logic operations: Memory Bit Line (MBL), Bit Select [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗

**Figure 2.** Figure 2: (a) Connecting cells with LL for gate operation. (b) Electrical equivalent of a logic gate. [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗

**Figure 3.** Figure 3: (a) CiM modeled as a thermal resistive network. [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗

**Figure 4.** Figure 4: INV STT Temperature and Power Density. Dashed line indicates 125 [PITH_FULL_IMAGE:figures/full_fig_p009_4.png] view at source ↗

**Figure 5.** Figure 5: VMUL STT Temperature and Power Density. Dashed line indicates 125 [PITH_FULL_IMAGE:figures/full_fig_p009_5.png] view at source ↗

**Figure 6.** Figure 6: NN STT Temperature and Power Density. Dashed line indicates 125 [PITH_FULL_IMAGE:figures/full_fig_p009_6.png] view at source ↗

**Figure 7.** Figure 7: INV SHE Temperature and Power Density [PITH_FULL_IMAGE:figures/full_fig_p010_7.png] view at source ↗

**Figure 8.** Figure 8: VMUL STT Temperature and Power Density [PITH_FULL_IMAGE:figures/full_fig_p010_8.png] view at source ↗

**Figure 9.** Figure 9: NN STT Temperature and Power Density [PITH_FULL_IMAGE:figures/full_fig_p010_9.png] view at source ↗

**Figure 10.** Figure 10: Maximum temperature for STT INVfx-100% under thermal throttling. Dashed line is 125 [PITH_FULL_IMAGE:figures/full_fig_p011_10.png] view at source ↗

read the original abstract

Computing-in-Memory (CiM) is a promising paradigm to address the memory bottleneck constraining traditional systems. Most power-efficient CiM variants can directly perform Boolean operations in non-volatile memory arrays. Higher microarchitectural activity due to CiM, however, can significantly increase power density (power per area) and result in thermal hotspots. In this paper, we provide a quantitative thermal characterization for CiM. We demonstrate that (i) the temperature remains mostly uniform due to lateral thermal conduction; (ii) the temperature increases linearly with the number of memory cells participating in computation; (iii) the temperature decreases linearly with the memory array size; (iv) the memory technology dictates the power density, hence the thermal characteristics.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

The paper gives simple linear thermal scaling rules for spintronic CiM from a basic model, but those rules lack any validation against real devices or layout details.

read the letter

The core point is that this work models temperature behavior in spintronic computing-in-memory arrays and reports four scaling observations: mostly uniform temperature from lateral conduction, linear rise with active cells, linear drop with array size, and dependence on the memory technology's power density. Those relationships could serve as quick design heuristics for thermal budgeting in this specific hardware style. The modeling approach itself is standard heat conduction applied to the CiM setting, which is a reasonable starting point for the niche. The authors correctly flag that higher activity in CiM raises power density and therefore thermal risk, and they isolate the uniformity effect as a potential positive for spintronics. That part is useful to note even if the numbers are preliminary. The main weakness is the complete absence of supporting evidence for the linearity claims. The abstract and stress-test note give no equations, no simulation parameters, no material property sources, and no comparison to fabricated arrays or measured temperatures. Without those, the reported linearities are just outputs of whatever assumptions went into the model, and real spintronic devices often have local variations in conductivity and power distribution that would break the scaling. The weakest assumption is that a simplified uniform model captures the dominant behavior; that needs checking. This paper is aimed at hardware architects and circuit designers working on non-volatile CiM variants who need early thermal estimates. A reader already familiar with thermal modeling in memory arrays will see the application but will also see the missing validation steps. It is coherent on its own terms and shows clear thinking about the problem, so it deserves a serious referee who can ask for the model details and any calibration data. I would send it to review rather than desk reject, with the expectation of major additions on methods and evidence.

Referee Report

2 major / 2 minor

Summary. The paper provides a quantitative thermal characterization of Computing-in-Memory (CiM) using spintronic memory arrays. It claims that (i) temperature remains mostly uniform due to lateral thermal conduction, (ii) temperature increases linearly with the number of active memory cells, (iii) temperature decreases linearly with array size, and (iv) the memory technology determines power density and thus thermal behavior.

Significance. If the modeling results hold under realistic conditions, the work supplies actionable scaling rules for array sizing and technology choice in thermally constrained spintronic CiM designs. The emphasis on lateral conduction and technology-specific power density is a useful contribution to the emerging CiM thermal literature.

major comments (2)

[Abstract] Abstract: the four central claims are stated without any supporting equations, simulation parameters, mesh details, or error bars. The linearity statements (ii) and (iii) cannot be evaluated for robustness without the underlying heat-equation formulation or boundary conditions.
[Thermal modeling section] Thermal modeling section (inferred from claims): the reported uniformity and linear scalings rest on an unvalidated simplified model that assumes uniform material properties, dominant lateral conduction, and absence of local hotspots from device geometry or interconnects. No comparison to measured temperatures in fabricated spintronic CiM prototypes or detailed layout extraction is provided, so any deviation from these assumptions would invalidate the scaling laws.

minor comments (2)

Specify the exact spintronic technologies (e.g., MTJ parameters, write currents) and array dimensions used in the simulations.
Add a brief discussion of how the model would change if vertical heat flow or material variation were included.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback on our manuscript. We address each major comment point by point below, indicating where revisions have been made to strengthen the presentation of our thermal modeling results.

read point-by-point responses

Referee: [Abstract] Abstract: the four central claims are stated without any supporting equations, simulation parameters, mesh details, or error bars. The linearity statements (ii) and (iii) cannot be evaluated for robustness without the underlying heat-equation formulation or boundary conditions.

Authors: We agree that the abstract, as a concise summary, does not include equations or detailed parameters. The heat diffusion equation, boundary conditions (including lateral conduction dominance), simulation parameters, and mesh details are fully described in the Thermal Modeling section, with error bars from repeated simulations shown in the results figures. To address the concern, we have revised the abstract to include a brief reference to the finite-element modeling framework and key assumptions used to establish the linearity. revision: yes
Referee: [Thermal modeling section] Thermal modeling section (inferred from claims): the reported uniformity and linear scalings rest on an unvalidated simplified model that assumes uniform material properties, dominant lateral conduction, and absence of local hotspots from device geometry or interconnects. No comparison to measured temperatures in fabricated spintronic CiM prototypes or detailed layout extraction is provided, so any deviation from these assumptions would invalidate the scaling laws.

Authors: The model solves the standard heat diffusion equation via finite-element analysis with material properties taken from published spintronic device literature. Uniform properties and dominant lateral conduction are appropriate first-order approximations for array-level thermal behavior and are stated explicitly. We have added a dedicated limitations subsection discussing potential local hotspots from geometry or interconnects and how they might affect the reported scalings. Experimental validation against fabricated prototypes is not included because the work is simulation-based and such specific thermal measurements for spintronic CiM are not available in the literature; we have noted this scope limitation and the need for future experimental corroboration. revision: partial

Circularity Check

0 steps flagged

No circularity identified; claims rest on unspecified thermal model without visible equations or derivation steps

full rationale

The provided text contains only high-level claims that temperature scales linearly with active cells and inversely with array size, attributed to a thermal model emphasizing lateral conduction and technology-dependent power density. No equations, model formulation, fitting procedure, or derivation chain appear in the abstract or surrounding text. Per hard rules, circularity requires explicit quotes showing reduction of a prediction to its inputs by construction; none exist here. The modeling assumptions may imply linearity, but this is not exhibited as a self-referential step. The paper is treated as self-contained against external benchmarks for this pass.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

No free parameters, axioms, or invented entities can be identified from the abstract alone.

pith-pipeline@v0.9.0 · 5428 in / 955 out tokens · 30264 ms · 2026-05-10T18:36:57.006987+00:00 · methodology

discussion (0)

Lean theorems connected to this paper

Citations machine-checked in the Pith Canon. Every link opens the source theorem in the public Lean library.

IndisputableMonolith/Cost/FunctionalEquation.lean washburn_uniqueness_aczel unclear

?

unclear
Relation between the paper passage and the cited Recognition theorem.

We divide the layer of active silicon ... into a grid of thermal nodes ... G T = P ... thermal conductance ... R_x = Δx / (k_t A_x)
IndisputableMonolith/Foundation/AlexanderDuality.lean alexander_duality_circle_linking unclear

?

unclear
Relation between the paper passage and the cited Recognition theorem.

temperature increases linearly with the number of memory cells ... decreases linearly with the memory array size

What do these tags mean?

matches: The paper's claim is directly supported by a theorem in the formal canon.
supports: The theorem supports part of the paper's argument, but the paper may add assumptions or extra steps.
extends: The paper goes beyond the formal theorem; the theorem is a base layer rather than the whole result.
uses: The paper appears to rely on the theorem as machinery.
contradicts: The paper's claim conflicts with a theorem or certificate in the canon.
unclear: Pith found a possible connection, but the passage is too broad, indirect, or ambiguous to say the theorem truly supports the claim.

Reference graph

Works this paper leans on

29 extracted references · 13 canonical work pages

[1]

Zamshed Chowdhury et al. 2017. Efficient in-memory processing using spintronics.IEEE CAL17, 1 (2017)

2017
[2]

Hüsrev Cılasun, Salonik Resch, Zamshed I Chowdhury, Erin Olson, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Keshab K Parhi, Jian-Ping Wang, Sachin S Sapatnekar, et al. 2021. Spiking neural networks in spintronic computational RAM.ACM Transactions on Architecture and Code Optimization (TACO)18, 4 (2021), 1–21

2021
[3]

Hüsrev Cılasun, Salonik Resch, Zamshed Iqbal Chowdhury, Erin Olson, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Jian-Ping Wang, Sachin S Sapatnekar, and Ulya Karpuzcu. 2020. Crafft: High resolution fft accelerator in spintronic computational ram. In2020 57th ACM/IEEE Design Automation Conference (DAC). IEEE, 1–6

2020
[4]

Hüsrev Cılasun, Salonik Resch, Zamshed I Chowdhury, Masoud Zabihi, Yang Lv, Brandon Zink, Jian-Ping Wang, Sachin S Sapatnekar, and Ulya R Karpuzcu. 2024. On Error Correction for Nonvolatile Processing-In-Memory. In2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA). IEEE, 678–692. doi:10.1109/ISCA59077.2024.00055

work page doi:10.1109/isca59077.2024.00055 2024
[5]

Neil Davey, Ray Frank, Steve Hunt, RG Adams, and Lee Calcraft. 2004. High capacity associative memory models-binary and bipolar representation. Procs of ASC 2004(2004)

2004
[6]

Mahoney, and Kurt Keutzer

Amir Gholami, Zhewei Yao, Sehoon Kim, Coleman Hooper, Michael W. Mahoney, and Kurt Keutzer. 2024. AI and Memory Wall .IEEE Micro44, 03 (May 2024). doi:10.1109/MM.2024.3373763

work page doi:10.1109/mm.2024.3373763 2024
[7]

West, Karina Torres-Castro, Nathan Swami, Samira Khan, and Mircea Stan

Jun-Han Han, Robert E. West, Karina Torres-Castro, Nathan Swami, Samira Khan, and Mircea Stan. 2021. Power and Thermal Modeling of In-3D-Memory Computing. In2021 International Symposium on Devices, Circuits and Systems (ISDCS). 1–4. doi:10.1109/ISDCS52006.2021.9397913

work page doi:10.1109/isdcs52006.2021.9397913 2021
[8]

Barak Hoffer and Shahar Kvatinsky. 2022. Performing Stateful Logic Using Spin-Orbit Torque (SOT) MRAM. InNANO. IEEE. Computing In Spintronic Memory: A Thermal Perspective 13

2022
[9]

J J Hopfield. 1982. Neural networks and physical systems with emergent col- lective computational abilities. InProceedings of the National Academy of Sciences of the United States of America, Vol. 79. PNAS, 2554–2558. doi:10.1073/pnas.79.8.2554

work page doi:10.1073/pnas.79.8.2554 1982
[10]

2023.2023 IEEE International Roadmap for Devices and Systems (IRDS)

IEEE International Roadmap for Devices and Systems (IRDS). 2023.2023 IEEE International Roadmap for Devices and Systems (IRDS). Technical Report. IEEE. $https://irds.ieee.org/images/files/pdf/2023/2023IRDS_BC.pdf$

work page arXiv 2023
[11]

Mohsen Imani, Saransh Gupta, Yeseong Kim, and Tajana Rosing. 2019. Floatpim: In-memory acceleration of deep neural network training with high precision. InProceedings of the 46th International Symposium on Computer Architecture. 802–815

2019
[12]

Unobserved Corner

Andrew B. Kahng, Uday Mallappa, Lawrence Saul, and Shangyuan Tong. 2019. "Unobserved Corner" Prediction: Reducing Timing Analysis Effort for Faster Design Convergence in Advanced-Node Design. In2019 Design, Automation & Test in Europe Conference & Exhibition (DATE). 168–173. doi:10.23919/DATE.2019.8715102

work page doi:10.23919/date.2019.8715102 2019
[13]

Marcel Khalifa, Rotem Ben-Hur, Ronny Ronen, Orian Leitersdorf, Leonid Yavits, and Shahar Kvatinsky. 2021. FiltPIM: In-memory filter for DNA sequencing. In2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS). IEEE, 1–4

2021
[14]

Yu-Ching Liao, Chenyun Pan, and Azad Naeemi. 2020. Benchmarking and Optimization of Spintronic Memory Arrays.IEEE Journal on Exploratory Solid-State Computational Devices and Circuits6, 1 (2020), 9–17. doi:10.1109/JXCDC.2020.2999270

work page doi:10.1109/jxcdc.2020.2999270 2020
[15]

Jeffry Louis et al. 2019. Performing memristor-aided logic (MAGIC) using STT-MRAM. InICECS

2019
[16]

Hamid Nejatollahi, Saransh Gupta, Mohsen Imani, Tajana Simunic Rosing, Rosario Cammarota, and Nikil Dutt. 2020. Cryptopim: In-memory acceleration for lattice-based cryptographic hardware. In2020 57th ACM/IEEE Design Automation Conference (DAC). IEEE, 1–6

2020
[17]

Salonik Resch, Hüsrev Cılasun, Masoud Zabihi, Zamshed Chowdhury, Zhengyang Zhao, Jian-Ping Wang, Sachin S Sapatnekar, and Ulya Karpuzcu
[18]

In2023 IEEE International Conference on Rebooting Computing (ICRC)

PimCity: A Compute in Memory Substrate featuring both Row and Column Parallel Computing. In2023 IEEE International Conference on Rebooting Computing (ICRC). IEEE, 1–10
[19]

Salonik Resch, S Karen Khatamifard, Zamshed I Chowdhury, Masoud Zabihi, Zhengyang Zhao, Husrev Cilasun, Jian-Ping Wang, Sachin S Sapatnekar, and Ulya R Karpuzcu. 2020. MOUSE: Inference in non-volatile memory for energy harvesting applications. In2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 400–414

2020
[20]

Stan, Wei Huang, Sivakumar Velusamy, Karthik Sankaranarayanan, and David Tarjan

Kevin Skadron, Mircea R. Stan, Wei Huang, Sivakumar Velusamy, Karthik Sankaranarayanan, and David Tarjan. 2003. Temperature-aware microarchitecture. InProceedings of the 30th Annual International Symposium on Computer Architecture(San Diego, California)(ISCA ’03). Association for Computing Machinery, New York, NY, USA, 2–13. doi:10.1145/859618.859620

work page doi:10.1145/859618.859620 2003
[21]

Stephens, Skylar Y

Zachary D. Stephens, Skylar Y. Lee, Faraz Faghri, Roy H. Campbell, Chengxiang Zhai, Miles J. Efron, Ravishankar Iyer, Michael C. Schatz, Saurabh Sinha, and Gene E. Robinson. 2015. Big Data: Astronomical or Genomical?PLOS Biology13, 7 (07 2015), 1–11. doi:10.1371/journal.pbio.1002195

work page doi:10.1371/journal.pbio.1002195 2015
[22]

Nishil Talati et al. 2016. Logic design within memristive memories using memristor-aided loGIC (MAGIC).IEEE Transactions on Nanotechnology15, 4 (2016)

2016
[23]

Simon Van Beek, Kaiming Cai, Siddharth Rao, Ganesh Jayakumar, Sebastien Couet, Nico Jossart, Adrian Chasin, and Gouri Sankar Kar. 2022. MTJ degradation in SOT-MRAM by self-heating-induced diffusion. In2022 IEEE International Reliability Physics Symposium (IRPS). 4A.2–1–4A.2–4. doi:10.1109/IRPS48227.2022.9764459

work page doi:10.1109/irps48227.2022.9764459 2022
[24]

Igor Wallossek. 2024. Best thermal paste database and charts - paste versus paste comparison, reviews and durability for CPU and GPU. https: //www.igorslab.de/en/the-worlds-first-interactive-thermal-paste-database-real-measurement-data-material-analysis-and-objective-fact-chec

2024
[25]

Paul (Ed) Wesling. 2023. Heterogeneous integration roadmap 2023 edition Chap 20.Heterogeneous Integration Roadmap(2023)

2023
[26]

Masoud Zabihi, Zamshed Iqbal Chowdhury, Zhengyang Zhao, Ulya R Karpuzcu, Jian-Ping Wang, and Sachin S Sapatnekar. 2018. In-memory processing on the spintronic CRAM: From hardware design to application mapping.IEEE Trans. Comput.68, 8 (2018), 1159–1173

2018
[27]

Masoud Zabihi, Zhengyang Zhao, Mahendra DC, Zamshed Chowdhury, Salonik Resch, Thomas Peterson, Ulya R Karpuzcu, Jian-Ping Wang, and Sachin S Sapatnekar. 2019. Using Spin-Hall MTJs to Build an Energy-Efficient In-memory Computation Platform. In20th International Symposium on Quality Electronic Design (ISQED). IEEE, 52–57. doi:10.1109/ISQED.2019.8697377

work page doi:10.1109/isqed.2019.8697377 2019
[28]

Kumar, and Sachin S

Yong Zhan, Sanjay V. Kumar, and Sachin S. Sapatnekar. 2008. Thermally Aware Design.Foundations and Trends®in Electronic Design Automation2, 3 (2008), 255–370. doi:10.1561/1000000007

work page doi:10.1561/1000000007 2008
[29]

Xue Zhang, Guangjun Zhang, Lijie Shen, Pingping Yu, and Yanfeng Jiang. 2020. Life-time degradation of STT-MRAM by self-heating effect with TDDB model.Solid-State Electronics173 (2020), 107878. doi:10.1016/j.sse.2020.107878

work page doi:10.1016/j.sse.2020.107878 2020