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arxiv: 2604.08672 · v1 · submitted 2026-04-09 · 🪐 quant-ph

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Hardware-Efficient Erasure Qubits With Superconducting Transmon Qutrits

Bao-Jie Liu , Ying-Ying Wang , Yu-Xin Wang , Manthan Badbaria , Shruti Puri , Chen Wang
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Pith reviewed 2026-05-10 17:09 UTC · model grok-4.3

classification 🪐 quant-ph
keywords erasure qubitstransmon qutritsquantum error correctionsuperconducting circuitslogical qubit lifetimemid-circuit detectionancilla SWAP gate
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The pith

Transmon qutrits serve as erasure qubits by encoding logical states in ground and second-excited levels and detecting relaxation via ancilla SWAP.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper shows that standard transmon qutrits can act as erasure qubits without extra hardware. Logical zero and one are stored in the ground and second excited states so that the dominant relaxation error becomes an erasure that an ancilla qubit can flag with a microwave-activated SWAP gate. Post-selected logical T1 exceeds 500 microseconds, ten times the physical qubit lifetime, while coherence reaches beyond 300 microseconds with dynamical decoupling and average Clifford infidelity stays near 10 to the minus four. The same ancilla can also perform parity checks, enabling heralded Bell states between erasure qubits. The scheme is presented as compatible with existing transmon arrays for fault-tolerant quantum error correction.

Core claim

Encoding logical states in the ground and second excited states of a transmon qutrit converts dominant relaxation into detectable erasures that a microwave-activated two-qutrit SWAP gate with an ancilla can identify, producing a post-selected logical T1 lifetime above 500 microseconds and coherence times above 300 microseconds.

What carries the argument

The microwave-activated two-qutrit SWAP gate between a data qutrit and ancilla that converts relaxation from the second excited state into a detectable erasure while leaving the logical subspace intact.

Load-bearing premise

The dominant errors are relaxation processes that the microwave-activated SWAP gate can turn into erasures without adding comparable new decoherence or control errors.

What would settle it

A measurement in which the post-selected logical T1 fails to exceed the physical T1 by roughly a factor of ten, or in which the observed erasure rate accounts for substantially less than the physical relaxation rate.

Figures

Figures reproduced from arXiv: 2604.08672 by Bao-Jie Liu, Chen Wang, Manthan Badbaria, Shruti Puri, Ying-Ying Wang, Yu-Xin Wang.

Figure 1
Figure 1. Figure 1: FIG. 1 [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2 [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: c shows coherence times of 301(22) µs and 299(19) µs when the qubit is initialized in logical | + X⟩ and | − X⟩ states, respectively; initializing in | ± Y ⟩ states produces similar coherence times (not shown here). The observed short-time linear decays of all six cardinal logical states towards a maximally mixed state and the symmetry between | ± X⟩ and | ± Y ⟩ states suggest a simple (Mako￾vian) Pauli lo… view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4 [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: FIG. 5 [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗
read the original abstract

Quantum error correction using erasure qubits offers higher fault-tolerant thresholds and improved scaling by converting dominant physical errors into detectable erasures. In superconducting circuits, erasure qubits can be constructed using the dual-rail approach, which, however, requires additional qubit-count overhead and tailored coupling elements. Here, we demonstrate a hardware-efficient scheme that operates transmon qutrits as erasure qubits, which is compatible with standard superconducting circuit-QED hardware. The logical states $\ket{0_\text{L}}$ and $\ket{1_\text{L}}$ are represented by the ground and second excited states, while the dominant relaxation errors can be detected via an ancilla qubit using a microwave-activated two-qutrit SWAP gate. We demonstrate a logical qubit $T_1$ lifetime exceeding $500\,\mu\mathrm{s}$, post-selected with repeated mid-circuit erasure detection, which is ten times longer than the $T_1$ time of the transmon physical qubit. Coherence times beyond $300\,\mu\mathrm{s}$ are achieved using dynamical decoupling. Single-qubit gate operations reach average Clifford gate infidelity on the order of $10^{-4}$. We further demonstrate dual-purposing an ancilla qubit for both erasure detection and parity checking, showing heralded generation of Bell states between erasure qubits. These results suggest that mainstream architectures of transmon qubit arrays may already be capable of implementing erasure-based QEC strategies for hardware-efficient fault-tolerant quantum computing.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The paper experimentally demonstrates a hardware-efficient erasure qubit using a transmon qutrit in superconducting circuits, encoding logical states in the ground and second-excited levels with relaxation errors converted to detectable erasures via a microwave-activated two-qutrit SWAP gate to an ancilla. Key results include a post-selected logical T1 lifetime exceeding 500 μs (claimed 10x longer than the physical qubit T1), coherence times beyond 300 μs with dynamical decoupling, single-qubit Clifford gate infidelities of order 10^{-4}, and dual use of the ancilla for erasure detection plus parity checks to generate heralded Bell states between erasure qubits.

Significance. If the lifetime extension is robustly shown to arise from erasure conversion without confounding gate-induced errors, this provides a practical route to erasure-based QEC in standard transmon arrays without dual-rail overhead, potentially raising thresholds and improving scaling. The mid-circuit detection and ancilla dual-purposing are concrete strengths for integration into existing hardware.

major comments (2)
  1. [Results (logical qubit lifetime)] Results section on logical T1 measurement: The central claim of a post-selected logical T1 >500 μs (10x physical) via repeated mid-circuit erasure detection requires an explicit error budget for the microwave-activated SWAP gate, including its duration, process fidelity for mapping relaxation from |2_L> to ancilla excitation, and any added relaxation/dephasing rates on the qutrit states. Without these, the observed extension cannot be unambiguously attributed to erasure protection rather than a mixture with gate-induced decoherence, as the abstract provides no such numbers despite reporting single-qubit infidelities.
  2. [Gate operations and error analysis] Section on two-qutrit gate characterization: The assumption that the SWAP reliably converts dominant relaxation errors without introducing comparable new decoherence is load-bearing for the 10x gain claim, yet the manuscript (per abstract) details only single-qubit gates at ~10^{-4} infidelity and omits quantitative SWAP metrics or controls comparing decay with/without the detection protocol.
minor comments (2)
  1. [Abstract] Abstract: The phrasing 'average Clifford gate infidelity on the order of 10^{-4}' is imprecise; reporting the exact average value, number of gates measured, and specific Clifford set would improve clarity and allow direct comparison to other works.
  2. [Throughout manuscript] Notation: Ensure consistent definition and use of logical states |0_L> and |1_L> (and |2_L> for the erasure level) across all sections, figures, and equations to avoid ambiguity in the encoding description.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the thorough review and constructive feedback on our manuscript. We appreciate the recognition of the potential significance of our hardware-efficient erasure qubit demonstration. We address the major comments below and will revise the manuscript accordingly to incorporate additional details on the gate characterization and error analysis.

read point-by-point responses

  1. Referee: Results section on logical T1 measurement: The central claim of a post-selected logical T1 >500 μs (10x physical) via repeated mid-circuit erasure detection requires an explicit error budget for the microwave-activated SWAP gate, including its duration, process fidelity for mapping relaxation from |2_L> to ancilla excitation, and any added relaxation/dephasing rates on the qutrit states. Without these, the observed extension cannot be unambiguously attributed to erasure protection rather than a mixture with gate-induced decoherence, as the abstract provides no such numbers despite reporting single-qubit infidelities.

    Authors: We agree with the referee that an explicit error budget is essential for rigorously attributing the observed lifetime extension to the erasure conversion mechanism. Although the full manuscript provides characterization of the two-qutrit SWAP gate, we acknowledge that a consolidated error budget was not presented in sufficient detail. In the revised version, we will add a dedicated subsection in the Results section detailing the SWAP gate duration, its process fidelity for the relaxation mapping, and any induced decoherence rates. We will also include a breakdown of error contributions and comparisons of decay rates with and without the detection protocol to demonstrate that the lifetime extension is due to erasure protection. revision: yes

  2. Referee: Section on two-qutrit gate characterization: The assumption that the SWAP reliably converts dominant relaxation errors without introducing comparable new decoherence is load-bearing for the 10x gain claim, yet the manuscript (per abstract) details only single-qubit gates at ~10^{-4} infidelity and omits quantitative SWAP metrics or controls comparing decay with/without the detection protocol.

    Authors: We thank the referee for this observation. The manuscript includes a section on the two-qutrit gate operations, but we recognize the need for more prominent quantitative metrics and explicit control experiments. In the revision, we will expand this section to provide full quantitative SWAP metrics and add direct comparisons of the logical decay rates with and without the mid-circuit erasure detection. This will confirm that the SWAP gate does not introduce decoherence levels that could explain the observed improvement. revision: yes

Circularity Check

0 steps flagged

No circularity: experimental demonstration with direct measurements

full rationale

The paper reports experimental results on transmon qutrits implementing erasure qubits via a microwave-activated SWAP gate for erasure detection. The central claims (logical T1 >500 μs post-selected, 10x physical T1, coherence >300 μs, gate infidelities ~10^{-4}) are presented as outcomes of direct measurements and post-selection on hardware, not as predictions derived from equations or models that reduce to the inputs. No self-definitional loops, fitted parameters renamed as predictions, or load-bearing self-citations appear in the derivation chain; the work is self-contained against external benchmarks via reported data. The skeptic concern about SWAP-induced decoherence is a question of experimental attribution and error budgeting, not circularity in any claimed derivation.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The demonstration relies on established circuit QED principles rather than new theoretical constructs.

axioms (1)
  • domain assumption Standard transmon qutrit energy level structure and microwave control assumptions hold.
    The encoding and SWAP gate operation presuppose known superconducting circuit physics.

pith-pipeline@v0.9.0 · 5574 in / 1189 out tokens · 68659 ms · 2026-05-10T17:09:45.201496+00:00 · methodology

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Reference graph

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