arxiv: 2604.08810 · v1 · submitted 2026-04-09 · 💻 cs.CV · cs.LG

Recognition: unknown

R2G: A Multi-View Circuit Graph Benchmark Suite from RTL to GDSII

Zewei Zhou , Jiajun Zou , Jiajia Zhang , Ao Yang , Ruichao He , Haozheng Zhou , Ao Liu , Jiawei Liu , Leilei Jin , Shan Shen , Daying Sun

Authors on Pith no claims yet

Pith reviewed 2026-05-10 16:57 UTC · model grok-4.3

classification 💻 cs.CV cs.LG

keywords circuit graphsgraph neural networksphysical designbenchmark suiteRTL to GDSIImulti-view representationsEDA automation

0 comments

The pith

View choice in circuit graph representations affects GNN accuracy more than the choice of GNN model.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces R2G, a benchmark suite that converts the same 30 open-source circuit designs into five different graph views spanning synthesis, placement, and routing. Each view carries identical attribute information but attaches those features to nodes, edges, or subgraphs in stage-specific ways. Experiments with three GNN architectures show that swapping the graph view changes test R² by more than 0.3 for any fixed model, while swapping the model inside one view produces smaller gains. Node-centric views turn out to generalize best from placement to routing tasks, and a three- or four-layer decoder head is enough to drive predictions to R² above 0.99. The suite supplies loaders, splits, and metrics so future work can test new models under controlled representation conditions.

Core claim

R2G supplies five stage-aware circuit-graph views that encode the same attributes yet differ only in feature attachment points. Systematic evaluation on GINE, GAT, and ResGatedGCN models reveals that representation choice produces larger accuracy swings than architecture choice, node-centric attachments generalize across placement and routing, and decoder depth of three to four layers converts divergent runs into near-perfect predictions with R² exceeding 0.99.

What carries the argument

Five stage-aware graph views with information parity, each attaching the same attribute set to different structural elements of the circuit netlist.

If this is right

Selecting the graph view alone can raise prediction R² by more than 0.3 without any change to the underlying GNN.
Node-centric views provide the strongest cross-stage generalization for both placement and routing tasks.
Increasing decoder-head depth to three or four layers is sufficient to reach R² greater than 0.99 on these graphs.
Future physical-design models can be compared fairly only after fixing the graph view, because representation effects otherwise confound architecture comparisons.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

EDA tool flows could prioritize graph-construction pipelines over repeated architecture search, because representation gains appear larger.
The same multi-view discipline might apply to other netlist-derived tasks such as timing or power estimation where stage-specific feature attachment has not yet been isolated.
If new open-source designs are added with different technology nodes, the benchmark can test whether the observed dominance of node-centric views persists beyond the current 30 cores.

Load-bearing premise

The five views truly preserve identical information content and the synthesis-to-routing pipeline introduces no hidden biases from tool choices or IP core selection.

What would settle it

A controlled experiment in which the same GNN is retrained on each view while forcing identical node and edge feature sets; if the R² gap across views shrinks below 0.1, the claim that view choice dominates would be falsified.

Figures

Figures reproduced from arXiv: 2604.08810 by Ao Liu, Ao Yang, Daying Sun, Haozheng Zhou, Jiajia Zhang, Jiajun Zou, Jiawei Liu, Leilei Jin, Ruichao He, Shan Shen, Zewei Zhou.

**Figure 2.** Figure 2: OpenROAD RTL-to-GDSII post-end flow including [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗

**Figure 3.** Figure 3: Original circuit schematic (a) and five complementary circuit graph views (b–f) used in R2G: (b) all-elements-as-nodes, (c) [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗

read the original abstract

Graph neural networks (GNNs) are increasingly applied to physical design tasks such as congestion prediction and wirelength estimation, yet progress is hindered by inconsistent circuit representations and the absence of controlled evaluation protocols. We present R2G (RTL-to-GDSII), a multi-view circuit-graph benchmark suite that standardizes five stage-aware views with information parity (every view encodes the same attribute set, differing only in where features attach) over 30 open-source IP cores (up to $10^6$ nodes/edges). R2G provides an end-to-end DEF-to-graph pipeline spanning synthesis, placement, and routing stages, together with loaders, unified splits, domain metrics, and reproducible baselines. By decoupling representation choice from model choice, R2G isolates a confound that prior EDA and graph-ML benchmarks leave uncontrolled. In systematic studies with GINE, GAT, and ResGatedGCN, we find: (i) view choice dominates model choice, with Test R$^2$ varying by more than 0.3 across representations for a fixed GNN; (ii) node-centric views generalize best across both placement and routing; and (iii) decoder-head depth (3--4 layers) is the primary accuracy driver, turning divergent training into near-perfect predictions (R$^2$$>$0.99). Code and datasets are available at https://github.com/ShenShan123/R2G.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

R2G supplies a practical new benchmark suite for multi-view circuit graphs with controlled comparisons, but the information-parity claim needs more explicit checks to fully support the view-dominance results.

read the letter

R2G gives a standardized benchmark that converts 30 open-source IP cores into five stage-aware graph views from RTL through GDSII, complete with loaders, unified splits, and baselines for three GNNs. The main new piece is the end-to-end DEF-to-graph pipeline plus the claim that the views differ only in feature attachment while keeping the same attribute set. The experiments then show view choice moving test R² by more than 0.3 for a fixed model, node-centric views generalizing better, and decoder depth driving most of the accuracy gains up to R² > 0.99. That directly tackles the uncontrolled representation confound in earlier EDA-GNN papers. The comparisons are systematic and the released code makes the numbers checkable, which is useful. The central claims rest on the parity assumption and the representativeness of the 30 cores. The paper asserts parity through the pipeline but does not include side-by-side attribute tables or explicit verification that every view retains gate types, timing, congestion signals, and connectivity without loss. If some views drop attributes during conversion, the R² gaps could partly reflect information differences rather than attachment point alone. The single tool flow across cores also leaves open the chance that splits do not isolate synthesis or routing biases. This work is aimed at researchers applying GNNs to physical design tasks who need a common testbed. It is worth sending to peer review because the resource and the empirical patterns are concrete enough to be refined rather than rejected outright.

Referee Report

1 major / 3 minor

Summary. The paper introduces the R2G benchmark suite, which standardizes five stage-aware circuit-graph views (with claimed information parity) derived from 30 open-source IP cores via an end-to-end DEF-to-graph pipeline spanning synthesis, placement, and routing. It supplies loaders, unified splits, domain-specific metrics, and reproducible baselines using GINE, GAT, and ResGatedGCN. Experiments show that view choice dominates model choice (Test R² varies by >0.3 for fixed GNN), node-centric views generalize best across stages, and decoder-head depth (3-4 layers) drives near-perfect predictions (R² > 0.99).

Significance. If the central claims hold, R2G supplies a much-needed controlled benchmark for GNNs in physical design, isolating representation effects that prior EDA and graph-ML work leaves confounded. The open release of data, code, and baselines, together with systematic multi-architecture comparisons and concrete R² metrics, are concrete strengths that lower the barrier for reproducible research on congestion, wirelength, and related tasks.

major comments (1)

[Abstract and §3] Abstract and §3 (Views and Pipeline): The central claim that performance gaps are attributable to representation (rather than unequal attribute content) rests on 'information parity' (every view encodes the same attribute set, differing only in attachment point). The manuscript asserts this via the shared DEF-to-graph pipeline but provides no explicit verification—e.g., no table or statistics confirming that gate types, netlist connectivity, timing, and congestion signals are identically present across all five views. Without this check, the reported R² differences (>0.3) could reflect information loss in some views rather than the intended confound.

minor comments (3)

[§5] §5 (Experiments): The description of unified splits and any data exclusion criteria for the 30 IP cores is brief; adding explicit details on train/validation/test construction and size-based filtering would improve defensibility of the generalization claims.
[Figure 3] Figure 3 (or equivalent results table): The R² values are reported to two decimals; showing standard deviation across seeds or runs would better convey stability of the 'near-perfect' (R² > 0.99) regime.
[§3] Notation: The distinction between 'node-centric' and other views is clear in text but could be reinforced with a small summary table listing attachment points and feature dimensions for each view.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the positive evaluation and the constructive comment on the information-parity claim. We address the concern point by point below.

read point-by-point responses

Referee: [Abstract and §3] Abstract and §3 (Views and Pipeline): The central claim that performance gaps are attributable to representation (rather than unequal attribute content) rests on 'information parity' (every view encodes the same attribute set, differing only in attachment point). The manuscript asserts this via the shared DEF-to-graph pipeline but provides no explicit verification—e.g., no table or statistics confirming that gate types, netlist connectivity, timing, and congestion signals are identically present across all five views. Without this check, the reported R² differences (>0.3) could reflect information loss in some views rather than the intended confound.

Authors: We agree that an explicit verification would strengthen the presentation. The information parity follows directly from the shared DEF-to-graph pipeline described in §3: all five views are generated from the identical DEF file and extract the same attribute set (gate types, netlist connectivity, timing arcs, congestion signals, etc.), differing solely in attachment point (node-centric vs. edge-centric) and stage-specific structural encoding. To address the referee’s request, we will insert a new table in the revised §3 that enumerates the attribute schema for each view together with summary statistics (e.g., attribute counts and value distributions) confirming equivalence. This addition will be purely expository and will not alter any experimental results or conclusions. revision: yes

Circularity Check

0 steps flagged

No circularity: benchmark supplies independent data, loaders, and empirical baselines

full rationale

The paper introduces a new multi-view circuit-graph dataset and pipeline over 30 IP cores, then reports direct empirical measurements (Test R² differences across views and models, decoder depth effects) on that data. No derivation, equation, or central claim reduces by construction to a parameter fitted inside the paper or to a self-citation chain; the information-parity assertion is a design statement about the DEF-to-graph conversion rather than a fitted or renamed result. The reported findings are falsifiable measurements on the released splits and therefore self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The work rests on standard assumptions about graph construction from EDA netlists and the applicability of message-passing GNNs; no new entities or heavily fitted parameters are introduced as load-bearing elements.

axioms (1)

domain assumption GNN message passing can capture relevant circuit properties for prediction tasks when graphs are constructed from DEF files
Invoked when applying GINE, GAT, and ResGatedGCN to the generated views for congestion and wirelength tasks.

pith-pipeline@v0.9.0 · 5593 in / 1244 out tokens · 81628 ms · 2026-05-10T16:57:45.604901+00:00 · methodology

discussion (0)

Reference graph

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