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arxiv: 2604.11333 · v1 · submitted 2026-04-13 · ⚛️ physics.app-ph · cond-mat.mtrl-sci

Recognition: unknown

ALD W-Doped SnO₂ TFTs for Indium-Free BEOL Electronics

Mansi Anil Patil (1) , Devarshi Dhoble (1) , Shivaram Kubakaddi (1) , Mamta Raturi (1) , Marco A Villena (2) , Gaurav Thareja (2) , Saurabh Lodha (1) ((1) Department of Electrical Engineering , Indian Institute of Technology Bombay
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Mumbai India (2) Department of Electronics Computer Technology Faculty of Sciences University of Granada Fuentenueva Avenue s/n Granada Spain (3) Applied Materials Inc Santa Clara California USA)
Authors on Pith no claims yet

Pith reviewed 2026-05-10 15:41 UTC · model grok-4.3

classification ⚛️ physics.app-ph cond-mat.mtrl-sci
keywords thin-film transistorsatomic layer depositiontin oxidetungsten dopingback-end-of-lineindium-freeoxide semiconductorsBEOL electronics
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The pith

Low-temperature ALD of 10% tungsten-doped tin oxide produces indium-free TFTs with 10^9 on/off ratio and strong bias stability after brief oxygen annealing.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper establishes that tungsten-doped tin oxide thin-film transistors grown by atomic layer deposition at 150 degrees Celsius can achieve strong performance when doped at 10 percent tungsten. A brief post-fabrication annealing in oxygen at 300 degrees for five minutes boosts the on-off current ratio to one billion, cuts the subthreshold swing in half, and greatly reduces hysteresis and bias-induced shifts. Simulations confirm that charge trapping in the dielectric is the main source of remaining instability. These findings matter because they offer an indium-free route to add transistors on top of existing chips, supporting more compact three-dimensional electronics without needing scarce materials.

Core claim

TFTs with 10% W doping in SnOx channels deposited by ALD at 150°C, after 300°C O2 annealing for 5 minutes, achieve a subthreshold swing reduced by nearly 2 times, Ion/Ioff ratio of 10^9, hysteresis decreased by 3 times, and bias stress threshold shift of only 93 mV at 4 MV/cm. Kinetic Monte Carlo simulations attribute the remaining instability to charge trapping. This establishes low-temperature ALD W-doped SnO2 as a viable indium-free material for BEOL compatible transistors and monolithic 3D integration.

What carries the argument

The 10% tungsten-doped tin oxide channel deposited by atomic layer deposition at 150°C and enhanced by short oxygen annealing, which improves carrier control and reduces defects leading to better device metrics.

Load-bearing premise

The observed benefits of W doping and O2 annealing will persist when these transistors are built directly atop finished CMOS circuits without introducing damage or additional reliability problems at production scales.

What would settle it

Measuring significant degradation in performance or damage to underlying CMOS layers when fabricating the TFTs on actual integrated circuits would disprove the BEOL compatibility claim.

Figures

Figures reproduced from arXiv: 2604.11333 by (2) Department of Electronics, (3) Applied Materials Inc, California, Computer Technology, Devarshi Dhoble (1), Faculty of Sciences, Fuentenueva Avenue s/n, Gaurav Thareja (2), Granada, India, Indian Institute of Technology Bombay, Mamta Raturi (1), Mansi Anil Patil (1), Marco A Villena (2), Mumbai, Santa Clara, Saurabh Lodha (1) ((1) Department of Electrical Engineering, Shivaram Kubakaddi (1), Spain, University of Granada, USA).

Figure 1
Figure 1. Figure 1: FIG. 1. (a) 3D schematic illustration of the device architecture. (b) Optical microscope image of the [PITH_FULL_IMAGE:figures/full_fig_p004_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2. (a) XPS survey spectra of ALD W-doped SnO [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3. (a) Transfer characteristics (I [PITH_FULL_IMAGE:figures/full_fig_p007_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4. (a) Measured and Ginestra [PITH_FULL_IMAGE:figures/full_fig_p008_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: FIG. 5. (a) Time-dependent I [PITH_FULL_IMAGE:figures/full_fig_p010_5.png] view at source ↗
read the original abstract

This work reports back-end-of-line (BEOL) compatible, thin-film transistors (TFTs) with sub-10 nm tungsten-doped tin oxide (TWO) channels deposited by atomic layer deposition (ALD) at 150 $^\circ$C. TFTs with undoped SnO$_{\mathrm{x}}$, undoped WO$_{\mathrm{x}}$, and W-doped SnO$_{\mathrm{x}}$ channels with W concentrations of 5% and 10% were investigated. TFT with 10% W doping exhibited the best electrostatic control and overall device performance. Post-fabrication O$_{\mathrm{2}}$ annealing at 300 $^\circ$C for 5 minutes significantly enhanced device characteristics, reducing the subthreshold swing (SS) by nearly 2$\times$, increasing the I$_{\mathrm{on}}$/I$_{\mathrm{off}}$ ratio from $10^7$ to $10^9$, decreasing hysteresis by nearly 3$\times$ and positive bias stress-induced threshold shift by over 2$\times$ to a low value of 93 mV at a stress field of 4 MV/cm. Kinetic Monte Carlo simulations using Ginestra$^{\mathrm{TM}}$ support the experimental observations and attribute the bias instability to charge trapping in the gate dielectric and at the interface. This work demonstrates low-temperature ALD-grown TWO TFTs as a promising indium-free platform for BEOL and monolithic 3D integration.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 2 minor

Summary. The manuscript reports fabrication of back-end-of-line (BEOL) compatible thin-film transistors (TFTs) with sub-10 nm tungsten-doped tin oxide (TWO) channels grown by atomic layer deposition (ALD) at 150°C. Devices with undoped SnOx, undoped WOx, and W-doped channels at 5% and 10% W were compared; the 10% W variant showed best electrostatic control. A post-fabrication 300°C O2 anneal for 5 min improved subthreshold swing by ~2×, raised Ion/Ioff from 10^7 to 10^9, reduced hysteresis by ~3×, and lowered positive-bias-stress threshold shift to 93 mV at 4 MV/cm. Ginestra kinetic Monte Carlo simulations attribute the remaining instability to dielectric and interface charge trapping. The work positions low-temperature ALD TWO TFTs as a promising indium-free platform for BEOL and monolithic 3D integration.

Significance. If the thermal-budget compatibility holds, the concrete metrics (high Ion/Ioff, low SS, reduced hysteresis and stress shift) plus simulation backing would constitute a useful experimental demonstration of an indium-free oxide TFT route for BEOL electronics. The annealing-induced improvements and the trapping-based explanation of bias instability are clear strengths of the reported data set.

major comments (1)
  1. [Conclusion / BEOL compatibility discussion] The central claim that these TFTs constitute a 'promising indium-free platform for BEOL' is load-bearing yet rests on an untested assumption: that the 300°C/5 min O2 anneal (and the full TWO flow) can be performed on actual CMOS wafers without damaging interconnects or pre-existing devices. No data on via resistance, metal-line integrity, or shifts in underlying transistors after the anneal are provided; all metrics come from test substrates only.
minor comments (2)
  1. [Experimental methods] State the exact method (XPS, EDX, etc.) and any uncertainty used to determine the 5% and 10% W concentrations in the channel.
  2. [Results and discussion] Include error bars or standard deviations on the reported SS, Ion/Ioff, hysteresis, and ΔVth values, and clarify the number of devices measured per condition.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the detailed and constructive report. The single major comment is addressed point-by-point below. We have revised the manuscript to acknowledge the limitation while preserving the technical contribution of the low-temperature ALD TWO process.

read point-by-point responses

  1. Referee: The central claim that these TFTs constitute a 'promising indium-free platform for BEOL' is load-bearing yet rests on an untested assumption: that the 300°C/5 min O2 anneal (and the full TWO flow) can be performed on actual CMOS wafers without damaging interconnects or pre-existing devices. No data on via resistance, metal-line integrity, or shifts in underlying transistors after the anneal are provided; all metrics come from test substrates only.

    Authors: We agree that all electrical data were obtained on Si/SiO2 test substrates and that no direct measurements of via resistance, Cu-line integrity, or shifts in underlying CMOS transistors after the 300 °C/5 min O2 anneal are presented. The 150 °C ALD deposition and 300 °C anneal were deliberately chosen to lie well below the typical 400 °C BEOL thermal ceiling, and the Ginestra simulations confirm that the observed bias instability originates from dielectric/interface trapping rather than channel crystallization. In the revised manuscript we have (i) added an explicit limitations paragraph in the Discussion section stating that full BEOL integration studies remain future work, (ii) changed the abstract and conclusion phrasing from “promising indium-free platform” to “potential indium-free route whose thermal budget is compatible with BEOL processing,” and (iii) included a brief comparison to literature reports that similarly claim BEOL compatibility on the basis of process temperature alone. These changes make the scope of the present study clear without altering the reported device metrics or simulation results. revision: partial

Circularity Check

0 steps flagged

No circularity: experimental metrics and supporting simulation are independent of any fitted derivation

full rationale

The manuscript is a fabrication-and-measurement study of ALD TWO TFTs. All reported device metrics (SS, Ion/Ioff, hysteresis, PBS shift) are directly measured on fabricated devices before and after O2 anneal; the Ginestra KMC runs are used only to reproduce the observed threshold shifts under a charge-trapping model. No equations, ansatzes, or parameter fits are presented as predictions that reduce to the inputs by construction. No self-citations supply load-bearing uniqueness theorems or ansatzes. The central claim therefore rests on empirical data rather than any self-referential derivation chain.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

Experimental device paper with no theoretical derivation; relies on standard semiconductor physics assumptions for TFT operation and charge trapping models.

axioms (1)
  • domain assumption Standard assumptions of ALD growth uniformity and TFT electrostatic models hold for sub-10 nm channels.
    Invoked implicitly when reporting SS, Ion/Ioff, and bias stress metrics without additional justification.

pith-pipeline@v0.9.0 · 5673 in / 1390 out tokens · 42463 ms · 2026-05-10T15:41:40.305637+00:00 · methodology

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