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arxiv: 2604.13319 · v1 · submitted 2026-04-14 · 💻 cs.AR

Recognition: unknown

Tensor Memory Engine: On-the-fly Data Reorganization for Ideal Locality

Denis Hoornaert , Cole Strickler , Manos Athanassoulis , Marco Caccamo , Heechul Yun , Renato Mancuso
Authors on Pith no claims yet

Pith reviewed 2026-05-10 13:31 UTC · model grok-4.3

classification 💻 cs.AR
keywords tensor memory enginedata reorganizationcache localityhardware software co-designmemory walledge computingSoC FPGAdata-intensive applications
0
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The pith

A Tensor Memory Engine placed in the CPU data path can deliver ideal cache locality by fetching data and presenting it in a reorganized layout.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Modern data-intensive applications often suffer from poor memory locality or require extra memory to fix it, which limits performance as the memory wall grows. The paper shows how a dedicated hardware unit called the Tensor Memory Engine can be inserted directly into the path between CPU and memory. This unit fetches data from its original locations and supplies the CPU with the same data but laid out for perfect cache behavior. Computation continues to run on the CPU while the engine handles all the reorganization work, avoiding the need to rewrite software or duplicate data structures.

Core claim

The paper's central claim is that a Tensor Memory Engine can be added to commercially available SoC and FPGA platforms so that it accesses memory on behalf of the CPUs and composes a re-organized view of the memory layout, thereby supplying running applications with data that exhibits ideal cache locality while keeping all computation on the CPUs and clearly separating memory access from processing.

What carries the argument

The Tensor Memory Engine: a hardware component inserted in the CPUs' data path that fetches data from memory and supplies it to the processor in a reorganized layout chosen to maximize spatiotemporal cache locality.

Load-bearing premise

The Tensor Memory Engine can be built on existing SoC and FPGA hardware without adding new bottlenecks or breaking seamless integration with standard CPUs.

What would settle it

Measure cache miss rates and execution time for representative data-intensive workloads on an SoC or FPGA with the Tensor Memory Engine enabled versus disabled; if miss rates stay high or total performance drops, the locality benefit does not materialize.

Figures

Figures reproduced from arXiv: 2604.13319 by Cole Strickler, Denis Hoornaert, Heechul Yun, Manos Athanassoulis, Marco Caccamo, Renato Mancuso.

Figure 2
Figure 2. Figure 2: Overview of the system organization. seamlessly interacts with the PS-side caches by leveraging the PLIM paradigm—see Section 2. Software layer. We propose a set of APIs that allow end users to leverage TME easily and without specialized knowl￾edge. Said API is intentionally made opaque to abstract away hardware-specific technical details. This is achieved by im￾plementing a two-layer user/kernel software … view at source ↗
Figure 3
Figure 3. Figure 3: Abstract overview of TME’s integration in a PS-PL [PITH_FULL_IMAGE:figures/full_fig_p006_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: TME’s architecture overview. The ACE port is [PITH_FULL_IMAGE:figures/full_fig_p006_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: TME is able to offer (i) speedup by eliminating transformation time (Fig. 5a) and (ii) ideal locality decrease transient working set size (WSS) by avoiding materialization of intermediate layouts (Fig. 5b). 16 32 64 128 Tensor size (MB) 100 200 300 400 500 600 Bandwidth (MB/s) 2 34 2 3 4 2 3 4 2 3 4 TME bandwidth across element sizes uint8_t uint16_t uint32_t uint64_t [PITH_FULL_IMAGE:figures/full_fig_p01… view at source ↗
Figure 6
Figure 6. Figure 6: For smaller element sizes, more TME-DRAM trans [PITH_FULL_IMAGE:figures/full_fig_p010_6.png] view at source ↗
read the original abstract

The shift to data-intensive processing from the cloud to the edge has introduced new challenges and expectations for the next generation of intelligent computing systems. As the memory wall continues to grow, modern systems can only meet these performance expectations by displaying data access patterns that exhibit ideal layouts in memory and ideal spatiotemporal locality in caches. However, only a few data-intensive applications are characterized by ideal locality. Instead, most applications exhibit either (i) poor locality when naively implemented and must undergo costly redesigns and tuning or (ii) inflated memory footprint to offer proper locality. To address the aforementioned challenges, we propose a hardware/software co-designed approach that can be implemented on commercially available SoC/FPGA platforms. Our approach seamlessly inserts in the CPUs' data path a Tensor Memory Engine that provides data with an ideal cache locality to running applications by (i) accessing the memory on behalf of the CPUs and (ii) composing a re-organized view of the memory layout. Unlike in- and near-memory computing approaches, it sets itself apart by clearly decoupling computing and memory accesses; computation is still performed on CPUs while the data re-organization is delegated to the Tensor Memory Engine.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript proposes a hardware/software co-design called the Tensor Memory Engine (TME) that is inserted into the CPU data path on commercial SoC/FPGA platforms. The TME accesses memory on behalf of the CPUs and composes a re-organized view of the memory layout to deliver ideal cache locality to running applications, while all computation remains on the CPUs. This approach is positioned as distinct from in- and near-memory computing by decoupling memory reorganization from computation, aiming to address the memory wall for data-intensive edge and cloud workloads without requiring application redesigns or inflated memory footprints.

Significance. If the TME can be realized with the claimed seamless integration and locality benefits, it would represent a practical middle ground between conventional CPU-centric systems and emerging in-memory architectures, potentially reducing the performance gap for applications that currently suffer from poor locality. The explicit decoupling of concerns is a conceptual strength that could ease adoption on existing platforms. However, the complete absence of any implementation details, hardware description, simulation results, or performance data means the practical significance cannot yet be assessed.

major comments (2)
  1. [Abstract] Abstract: the central claim that the TME 'provides data with an ideal cache locality' and can be 'seamlessly' inserted without new bottlenecks is presented without any supporting quantitative model, latency analysis, or prototype results, leaving the load-bearing feasibility assertion unsubstantiated.
  2. [Proposed Approach] The manuscript provides no hardware architecture details (e.g., buffering strategy, address remapping logic, or integration with existing cache coherence protocols) for how on-the-fly reorganization is performed while maintaining correctness for arbitrary access patterns.
minor comments (2)
  1. The repeated use of 'ideal locality' and 'ideal cache locality' would benefit from a precise definition (e.g., in terms of compulsory/capacity/conflict misses or a target hit-rate metric) to allow future evaluation.
  2. No references to prior work on memory-side accelerators or data-layout engines are visible in the provided text; adding a related-work section would help situate the contribution.

Simulated Author's Rebuttal

2 responses · 1 unresolved

We thank the referee for the constructive feedback on our manuscript. We address each major comment below and outline the revisions we will make to clarify the conceptual nature of the TME proposal while strengthening the presentation.

read point-by-point responses

  1. Referee: [Abstract] Abstract: the central claim that the TME 'provides data with an ideal cache locality' and can be 'seamlessly' inserted without new bottlenecks is presented without any supporting quantitative model, latency analysis, or prototype results, leaving the load-bearing feasibility assertion unsubstantiated.

    Authors: We agree that the abstract presents the intended benefits at a high level without quantitative support. The manuscript is a conceptual hardware/software co-design proposal rather than an evaluated implementation. In the revised version, we will update the abstract to qualify the claims as design goals and add a dedicated discussion section providing a high-level analytical model of expected locality improvements and potential insertion overheads based on the described data-path integration. revision: yes

  2. Referee: [Proposed Approach] The manuscript provides no hardware architecture details (e.g., buffering strategy, address remapping logic, or integration with existing cache coherence protocols) for how on-the-fly reorganization is performed while maintaining correctness for arbitrary access patterns.

    Authors: The current manuscript emphasizes the system-level distinction of decoupling reorganization from computation. We acknowledge the absence of low-level hardware specifics. We will expand the Proposed Approach section with additional high-level architectural descriptions covering buffering concepts for on-the-fly access, logical address remapping to support arbitrary patterns, and high-level considerations for maintaining coherence and correctness through software-managed mappings. revision: yes

standing simulated objections not resolved
  • Providing concrete prototype results, full hardware descriptions, or simulation data, as the work remains at the conceptual proposal stage without an implemented or simulated prototype.

Circularity Check

0 steps flagged

No significant circularity detected in the Tensor Memory Engine proposal

full rationale

The paper presents a hardware/software co-design proposal for inserting a Tensor Memory Engine into the CPU data path to perform on-the-fly data reorganization while keeping computation on the CPU. No mathematical derivations, equations, parameter fittings, or self-citations appear in the provided text that would reduce any claim to its inputs by construction. The central argument explicitly decouples computing from memory accesses, targets commercial SoC/FPGA platforms, and contrasts with in/near-memory computing without invoking uniqueness theorems, ansatzes, or fitted predictions. The approach is self-contained as a descriptive design proposal rather than a closed-form derivation chain.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 1 invented entities

Based solely on the abstract, which introduces the TME as the key new entity without detailing free parameters or additional axioms.

axioms (1)
  • domain assumption Modern systems require ideal data layouts and spatiotemporal locality for performance.
    Stated in the abstract as the basis for the memory wall challenge.
invented entities (1)
  • Tensor Memory Engine no independent evidence
    purpose: To access memory on behalf of CPUs and provide re-organized data views for ideal cache locality.
    New hardware component proposed in the paper with no external validation mentioned.

pith-pipeline@v0.9.0 · 5521 in / 1309 out tokens · 97556 ms · 2026-05-10T13:31:54.085653+00:00 · methodology

discussion (0)

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