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arxiv: 2604.13523 · v1 · submitted 2026-04-15 · 💻 cs.AR

Recognition: unknown

ATLAAS: Automatic Tensor-Level Abstraction of Accelerator Semantics

Ruijie Gao , Haoran Jin , Jirong Yang , Nathaniel Bleier
Authors on Pith no claims yet

Pith reviewed 2026-05-10 12:36 UTC · model grok-4.3

classification 💻 cs.AR
keywords tensor acceleratorsemantic liftingISA specificationMLIR transformationcompiler backend generationRTL abstractionequivalence checking
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The pith

An 8-pass MLIR pipeline lifts bit-level accelerator descriptions to complete tensor-level ISA specifications.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper shows how to take low-level bit operations extracted from hardware descriptions and automatically raise them to high-level tensor operations such as matrix multiplies, saturating arithmetic, and multi-dimensional memory layouts. This automation replaces the previous manual writing of tensor ISA specs, which had been the main barrier to building full compiler stacks for new accelerators. If the lifting succeeds without accelerator-specific rules, it directly produces input for existing tools that generate compilers, simulators, and performance models. The work demonstrates the approach on two different accelerators, showing large reductions in description size and the recovery of features that hand-written specs had missed.

Core claim

Starting from bit-level LLVM IR produced by RTL extraction, the 8-pass pipeline progressively recovers MAC idioms, saturation semantics, multi-dimensional buffer organizations, and data layout transformations, emitting tensor ISA specifications that enable automatic software stack generation. On the Gemmini systolic array the pipeline reduces bit-level MLIR size by up to 92.9 percent on processing elements and 24-34 percent on controllers, while discovering omitted hardware features whose correctness is confirmed by Z3 equivalence proofs. The same unmodified pipeline succeeds on all four datapath modules of TVM's VTA processor, confirming that the abstraction steps are general.

What carries the argument

An 8-pass semantic lifting pipeline inside MLIR that transforms bit-level operations into tensor-level constructs such as MAC idioms, saturation, buffers, and layouts.

If this is right

  • Any accelerator whose RTL can be turned into LLVM IR can now receive a tensor ISA spec without manual documentation.
  • Compiler backends, simulators, and code generators become available automatically once the lifted spec exists.
  • Hardware features that were omitted from hand-written specs can be recovered and validated by equivalence checking.
  • The same lifting steps apply across systolic arrays and other datapath styles without per-accelerator changes.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Design teams could iterate on new accelerator RTL and immediately obtain a compiler stack for evaluation instead of writing specs by hand.
  • The recovered tensor specifications could serve as a neutral reference for comparing different hardware implementations of the same operator set.
  • If the lifting passes are made modular, they might be reused to abstract other intermediate representations beyond MLIR.

Load-bearing premise

The eight successive passes can reconstruct the full high-level tensor structure from bit-level IR without any accelerator-specific tuning and without dropping semantics.

What would settle it

Running the pipeline on a third accelerator whose hand-written tensor ISA is known to be complete, then checking whether the automatically produced spec either differs in observable behavior or fails to generate a working compiler backend.

Figures

Figures reproduced from arXiv: 2604.13523 by Haoran Jin, Jirong Yang, Nathaniel Bleier, Ruijie Gao.

Figure 1
Figure 1. Figure 1: Overview of the existing landscape. ATLAAS bridges [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: ATLAAS’s semantic lifting on a Gemmini PE: from [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: ATLAAS’s three-stage pipeline: RTL-to-MLIR ex [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: MLIR line counts before and after ATLAAS’s 8-pass [PITH_FULL_IMAGE:figures/full_fig_p006_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Cycle-level latency comparison between hand [PITH_FULL_IMAGE:figures/full_fig_p007_5.png] view at source ↗
read the original abstract

Numerous tensor accelerator designs have been proposed, yet most lack well-documented ISAs and compiler backends, limiting evaluation to a handful of operators. Recent work has shown that given a tensor-level ISA specification, complete software stacks including compiler backends can be automatically generated--but writing such specifications remains a manual, expert-driven process. We present ATLAAS, the first end-to-end MLIR-based pipeline that lifts RTL-extracted accelerator semantics to tensor ISA specifications. Starting from bit-level LLVM IR produced by prior architecture-level model extraction, ATLAAS applies an 8-pass semantic lifting pipeline that progressively recovers high-level tensor structure--MAC idioms, saturation semantics, multi-dimensional buffer organizations, and data layout transformations--emitting specifications that immediately enable automatic software stack generation through the ACT ecosystem. We evaluate ATLAAS on the Gemmini systolic-array accelerator, where the pipeline collapses bit-level MLIR by up to 92.9% on processing elements and 24-34% on controller modules. ATLAAS discovers hardware features omitted from the hand-written reference, with correctness validated via Z3 SMT equivalence proofs. Generality is confirmed on TVM's VTA processor, where the same pipeline lifts all four datapath modules without accelerator-specific changes, enabling an automated path from RTL to a performance-competitive compiler backend.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. ATLAAS presents the first end-to-end MLIR-based pipeline that lifts bit-level LLVM IR (extracted from RTL accelerator models) to high-level tensor ISA specifications via an 8-pass semantic lifting process. The passes progressively recover MAC idioms, saturation semantics, multi-dimensional buffers, and data-layout transformations, emitting specs that feed directly into the ACT ecosystem for automatic compiler-backend generation. Evaluation on Gemmini reports up to 92.9% collapse of bit-level MLIR on processing elements (24-34% on controllers) and discovery of omitted hardware features; the same untuned pipeline is shown to lift all four datapath modules of TVM's VTA, with Z3 SMT equivalence proofs used to validate correctness.

Significance. If the lifting pipeline is shown to be semantics-preserving and free of accelerator-specific tuning, the work would meaningfully reduce the manual effort required to obtain usable tensor ISA specifications, thereby enabling automated software-stack generation for a wider range of accelerators. The combination of an MLIR-based implementation, concrete size-reduction numbers, application to two distinct designs, and use of SMT-based validation constitutes a concrete engineering contribution; the reproducibility of the pipeline and the formal checks are particular strengths.

major comments (2)
  1. [§5 and §6] §5 (Gemmini evaluation) and §6 (VTA evaluation): the claim that the 8-pass pipeline recovers complete tensor structure 'without accelerator-specific changes' and 'without loss of semantics' rests on Z3 equivalence proofs, yet the manuscript does not state whether these proofs establish exhaustive functional equivalence (all operators, all input vectors, saturation boundaries, and layout transformations) or only equivalence on the newly discovered omitted features and sampled behaviors. If the latter, undetected semantic loss remains possible and directly weakens the 92.9% collapse claim.
  2. [§4] §4 (semantic lifting pipeline): the description of the eight passes does not provide a formal argument or invariant that each pass is semantics-preserving; without such an argument or an exhaustive equivalence check between the original bit-level IR and the final tensor spec, it is difficult to assess whether the progressive abstraction is total.
minor comments (2)
  1. [Table 1] Table 1 (Gemmini size-reduction results): the baseline 'bit-level MLIR' size should be reported alongside the post-lifting sizes so that the 92.9% figure can be independently verified.
  2. The manuscript would benefit from a short pseudocode or data-flow diagram of the eight passes to make the overall pipeline structure immediately clear to readers unfamiliar with MLIR dialects.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback on the validation scope and semantics preservation arguments. We agree that the manuscript would benefit from greater clarity on these points and will revise accordingly while preserving the core technical contributions.

read point-by-point responses

  1. Referee: [§5 and §6] §5 (Gemmini evaluation) and §6 (VTA evaluation): the claim that the 8-pass pipeline recovers complete tensor structure 'without accelerator-specific changes' and 'without loss of semantics' rests on Z3 equivalence proofs, yet the manuscript does not state whether these proofs establish exhaustive functional equivalence (all operators, all input vectors, saturation boundaries, and layout transformations) or only equivalence on the newly discovered omitted features and sampled behaviors. If the latter, undetected semantic loss remains possible and directly weakens the 92.9% collapse claim.

    Authors: The Z3 equivalence proofs were performed on the specific tensor operations recovered by the pipeline, including the omitted hardware features identified in Gemmini, along with representative operators, input vectors, saturation behaviors, and layout transformations. These checks confirm that the lifted specifications compute identical results to the original bit-level IR for the abstracted structures. We do not claim exhaustive verification over the entire input space or all boundary conditions, which would be intractable. The 92.9% collapse figure quantifies the reduction from replacing verified bit-level patterns with their tensor equivalents. We will revise §5 and §6 to explicitly delineate the scope of the proofs and note that they validate the recovered semantics. revision: partial

  2. Referee: [§4] §4 (semantic lifting pipeline): the description of the eight passes does not provide a formal argument or invariant that each pass is semantics-preserving; without such an argument or an exhaustive equivalence check between the original bit-level IR and the final tensor spec, it is difficult to assess whether the progressive abstraction is total.

    Authors: Each pass is implemented via MLIR rewrites that substitute equivalent higher-level constructs for lower-level bit operations while preserving dataflow, computation results, and memory semantics by construction. The end-to-end Z3 validation supports overall correctness. We acknowledge that the manuscript lacks an explicit statement of per-pass invariants. In the revision we will add a subsection to §4 that articulates the semantic invariants maintained by each pass (e.g., equivalence of arithmetic results, buffer layouts, and control flow) and describes their composition, thereby addressing the concern about total abstraction. revision: yes

Circularity Check

0 steps flagged

No circularity: empirical tool pipeline with external validation

full rationale

The paper presents ATLAAS as an 8-pass MLIR pipeline that lifts bit-level LLVM IR to tensor ISA specifications, with claims resting on measured collapse ratios (92.9% on PEs), discovery of omitted features, and Z3 SMT equivalence proofs on Gemmini and VTA. No mathematical derivations, equations, fitted parameters, or predictions are described. The central results are obtained by applying the pipeline to concrete accelerators and checking outputs against reference implementations via an external solver (Z3), which does not reduce to self-definition or self-citation chains. The pipeline description and evaluation are self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

The work relies on standard MLIR and LLVM IR infrastructure plus the ACT ecosystem; no new free parameters, axioms, or invented entities are introduced beyond the pipeline itself.

pith-pipeline@v0.9.0 · 5539 in / 1184 out tokens · 21054 ms · 2026-05-10T12:36:36.141416+00:00 · methodology

discussion (0)

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