arxiv: 2604.13624 · v1 · submitted 2026-04-15 · 💻 cs.ET

Recognition: unknown

DTCO Exploration of NOR-Type IGZO FeFETs for Read-Dominated Memories

Yang Xiang , Zhuo Chen , Nicolo Ronchi , Arvind Sharma , Fernando Garcia-Redondo , Subhali Subhechha , Attilio Belmonte , Maarten Rosmeulen

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Gouri Sankar Kar Dwaipayan Biswas Jan Van Houdt

Authors on Pith no claims yet

Pith reviewed 2026-05-10 12:13 UTC · model grok-4.3

classification 💻 cs.ET

keywords IGZO FeFETNOR memoryDTCOsneak currentread-centric workloadsBEOL integrationsensing margin3D FeNOR

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The pith

NOR-type IGZO FeFETs achieve 0.016 square micrometer SRAM-equivalent bitcells and sub-5 nanosecond random access for read-centric AI memories.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper investigates indium-gallium-zinc-oxide ferroelectric transistors arranged in NOR arrays as memory elements suited to workloads that read data far more often than they write it, such as AI inference. Through design-technology co-optimization the authors demonstrate that back-end-of-line versions of these devices can shrink their bitcell footprint across nodes to match the area of a ten-transistor SRAM cell at 0.016 square micrometers under 7-nanometer design rules while delivering random-access times below five nanoseconds. The work identifies a sensing-margin penalty caused by sneak currents that flow when cells sit in a negative threshold-voltage state, and shows that positive threshold-voltage engineering, for example by thinning the ferroelectric layer, removes the need for negative read-inhibition voltages. This approach matters because it offers a path to embed dense, fast read memory directly above logic layers without relying on front-end silicon processes.

Core claim

Back-end-of-line IGZO FeFETs in NOR configuration deliver a bitcell footprint of 0.016 um2 that equals ten-transistor SRAM area under 7-nm ground rules and support sub-5 ns random access latency despite writability limits. Sensing margins in the array are reduced by sneak currents tied to the negative program-state threshold voltage, which can be eliminated by shifting to positive threshold voltages through ferroelectric-layer thinning. In three-dimensional FeNOR stacks intended for storage-class memory the achievable density is further restricted by additional sneak paths formed by neighbor-channel shunting.

What carries the argument

Design-technology co-optimization of NOR-type IGZO FeFET bitcells that quantifies footprint scaling, access latency, and the sensing-margin degradation produced by sneak currents from negative-Vt states.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

Placing such BEOL memory directly above logic could cut the energy spent moving data in AI accelerators by shortening interconnect distances.
Additional isolation structures or material changes beyond layer thinning may be needed to control sneak currents in dense 3D stacks.
Success in read-heavy workloads could make this memory type competitive with other embedded options for edge inference or database acceleration.
The reported cross-node area scaling suggests the technology might continue to shrink in future process generations if the sneak-current issue is solved.

Load-bearing premise

The DTCO models and array simulations correctly predict physical sneak currents, sensing margins, and ferroelectric switching behavior without needing unstated material assumptions or post-simulation tuning.

What would settle it

Measurement of sneak current, read sensing margins, and random-access latency on a fabricated NOR IGZO FeFET array built at 7-nm ground rules, to determine whether sub-5 ns operation and adequate margins are obtained or whether negative-Vt penalties remain.

read the original abstract

InGaZnO (IGZO) channel FeFETs have attracted notable interest thanks to their advances in endurance. This work evaluates the viability of NOR-type IGZO FeFETs for readcentric AI inference workloads via design-technology cooptimization (DTCO). We demonstrate the cross-node bitcell footprint scalability of back-end-of-line (BEOL) IGZO FeFETs capable of delivering 10-A SRAM-equivalent area (0.016 um2) with 7-nm ground rules and reaching sub-5 ns random access latency despite writability challenges. We further identify the sensing margin penalty in NOR FeFET arrays arising from sneak current associated with the negative program-state Vt, which requires positive-Vt engineering in order to eliminate the unwanted negative voltage read inhibition - for example, by ferroelectric layer thinning. Last but not least, we elucidate the read margin implications on 3D FeNOR for storage-class memories (SCMs), with the 3D stacking density limited by additional sneak current from neighbor channel shunting.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

DTCO paper projects small NOR IGZO FeFET cells and fast reads for AI memory but the numbers rest on uncalibrated array models.

read the letter

This paper runs DTCO on NOR-type IGZO FeFETs aimed at read-heavy AI inference memory. It projects 0.016 µm² bitcells at 7 nm rules with sub-5 ns random access while flagging sneak-current limits from negative program Vt and neighbor shunting in 3D stacks. The main new angle is the explicit mapping of those array penalties onto read-dominated workloads and the suggestion that ferroelectric thinning can enforce positive Vt to cut read inhibition. That part is clear and identifies a practical constraint for anyone integrating these devices above CMOS. The work also sketches how stacking density gets capped by extra shunt paths, which is a useful flag for storage-class memory planning. The soft spot is exactly the one the stress-test note raises: the area, latency, and margin numbers come from compact models whose ferroelectric polarization, trap, and leakage parameters are not shown anchored to measured I-V, endurance, or retention curves for the actual BEOL IGZO stack. Without that calibration, the projections risk being optimistic if real parasitic leakage or switching behavior deviates. For a simulation-heavy DTCO study this is a moderate rather than fatal issue, but it does mean the claims need experimental cross-check before they guide tape-outs. The paper is aimed at device engineers and memory architects already working on FeFET or BEOL options for inference hardware. A reader in that niche will pick up concrete design knobs to watch. It deserves a serious referee because the topic is timely and the array-level analysis is focused, even if the modeling section needs tightening. I would send it for peer review and ask specifically for any validation plots or parameter sources that tie the models back to silicon.

Referee Report

3 major / 2 minor

Summary. The paper conducts a design-technology co-optimization (DTCO) analysis of NOR-type IGZO FeFETs for read-dominated AI inference memories. It demonstrates that these BEOL devices can scale to a bitcell footprint of 0.016 μm² (10x SRAM equivalent) with 7-nm ground rules and achieve sub-5 ns random access latency. The study highlights the sensing margin degradation due to sneak currents from negative program-state threshold voltages in NOR configurations, suggests ferroelectric layer thinning for positive-Vt engineering to mitigate read inhibition, and examines the additional sneak current from neighbor channel shunting that limits 3D stacking density for storage-class memory applications.

Significance. If the DTCO simulation results are accurate, this work is significant as it addresses key integration challenges for ferroelectric memories in high-density, read-intensive applications like AI inference. It offers concrete projections on area, latency, and array-level penalties, which can guide future device and circuit design. The identification of specific engineering solutions like layer thinning and the analysis of 3D implications provide actionable insights. The use of DTCO to explore cross-node scalability is a strength.

major comments (3)

[§3 (Device Modeling and DTCO Framework)] §3 (Device Modeling and DTCO Framework): The compact models for IGZO FeFETs, including ferroelectric polarization switching and trap distributions, are not calibrated against experimental I-V, endurance, or retention data for the specific BEOL stack. This is load-bearing for the central claims on sneak current penalties and sensing margins, as unanchored parameters could lead to optimistic projections of sub-5 ns latency and 3D density limits.
[§5.1 (Positive-Vt Engineering via Ferroelectric Thinning)] §5.1 (Positive-Vt Engineering via Ferroelectric Thinning): The analysis claims that thinning the ferroelectric layer enforces positive Vt without significant degradation, but no quantitative trade-off curves or endurance/retention simulations are provided to support this; the section only qualitatively discusses the approach, undermining the viability claim for eliminating negative voltage read inhibition.
[§6 (3D FeNOR Array Simulations)] §6 (3D FeNOR Array Simulations): The neighbor-channel shunting current in stacked 3D cells is modeled, but the paper does not specify the assumptions on inter-layer dielectric thickness or parasitic capacitances; this affects the read margin limits reported and requires clarification to assess the 3D stacking density projections.

minor comments (2)

[Figure 4] Figure 4 caption does not specify the read voltage or bias conditions used in the simulations.
[References] References section is missing citations to recent experimental work on IGZO FeFET endurance and BEOL integration.

Simulated Author's Rebuttal

3 responses · 0 unresolved

We thank the referee for the constructive and detailed feedback on our DTCO exploration of NOR-type IGZO FeFETs. We address each major comment point by point below. Revisions have been made to improve the manuscript's clarity, support for claims, and transparency of modeling assumptions.

read point-by-point responses

Referee: [§3 (Device Modeling and DTCO Framework)] §3 (Device Modeling and DTCO Framework): The compact models for IGZO FeFETs, including ferroelectric polarization switching and trap distributions, are not calibrated against experimental I-V, endurance, or retention data for the specific BEOL stack. This is load-bearing for the central claims on sneak current penalties and sensing margins, as unanchored parameters could lead to optimistic projections of sub-5 ns latency and 3D density limits.

Authors: We acknowledge that the compact models are not directly calibrated to experimental data from a fabricated specific BEOL IGZO FeFET stack, as this work is a forward-looking DTCO study rather than a device fabrication report. The models incorporate ferroelectric polarization switching and trap distributions drawn from established literature on IGZO FeFETs. In the revised manuscript, we will expand §3 with explicit citations to the source experimental datasets, a table of key model parameters, and a sensitivity analysis on parameters most relevant to sneak current and sensing margin to better substantiate the latency and density projections. revision: partial
Referee: [§5.1 (Positive-Vt Engineering via Ferroelectric Thinning)] §5.1 (Positive-Vt Engineering via Ferroelectric Thinning): The analysis claims that thinning the ferroelectric layer enforces positive Vt without significant degradation, but no quantitative trade-off curves or endurance/retention simulations are provided to support this; the section only qualitatively discusses the approach, undermining the viability claim for eliminating negative voltage read inhibition.

Authors: The referee is correct that §5.1 currently offers only a qualitative description of positive-Vt engineering through ferroelectric layer thinning. We will revise this section to include quantitative trade-off curves from our simulation framework, plotting ferroelectric thickness against Vt shift, read current, endurance, and retention characteristics. This addition will provide concrete data supporting the approach for mitigating read inhibition due to sneak currents. revision: yes
Referee: [§6 (3D FeNOR Array Simulations)] §6 (3D FeNOR Array Simulations): The neighbor-channel shunting current in stacked 3D cells is modeled, but the paper does not specify the assumptions on inter-layer dielectric thickness or parasitic capacitances; this affects the read margin limits reported and requires clarification to assess the 3D stacking density projections.

Authors: We agree that the assumptions for inter-layer dielectric thickness and parasitic capacitances in the 3D simulations should be explicitly documented. In the revised manuscript, we will add these details to §6, including the specific values employed (drawn from standard BEOL process assumptions), their sources, and a sensitivity analysis demonstrating their effect on the reported read margins and 3D stacking density limits. revision: yes

Circularity Check

0 steps flagged

No significant circularity detected in DTCO simulation claims

full rationale

The paper presents DTCO-based projections for IGZO FeFET bitcell scalability, latency, and read margins in NOR and 3D configurations. No load-bearing derivation steps, equations, or self-citations are identifiable in the abstract or described content that reduce predictions to fitted inputs by construction, self-definitional loops, or unverified author-unique theorems. The results are framed as outcomes of array simulations capturing sneak currents and ferroelectric behavior, which remain independent if the underlying compact models are anchored externally. This is the expected non-finding for a simulation-driven exploration paper whose central claims do not collapse into their own inputs.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Abstract supplies no explicit free parameters, axioms, or invented entities; typical DTCO work would include fitted ferroelectric parameters and process assumptions not listed here.

pith-pipeline@v0.9.0 · 5524 in / 1126 out tokens · 54010 ms · 2026-05-10T12:13:27.365957+00:00 · methodology

discussion (0)

Reference graph

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