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arxiv: 2604.14446 · v1 · submitted 2026-04-15 · 💻 cs.ET

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CMOS-integrated superparamagnetic tunnel junction-based p-bit

Advait Madhavan, Hideo Ohno, Jabez J. McClelland, Ju-Young Yoon, Nuno Cacoilo, Shun Kanai, Shunsuke Fukami, William A. Borders

Authors on Pith no claims yet

Pith reviewed 2026-05-10 11:14 UTC · model grok-4.3

classification 💻 cs.ET
keywords p-bitsuperparamagnetic tunnel junctionCMOS integrationprobabilistic computingtunnel junctionprobabilistic bithardware implementation
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The pith

Superparamagnetic tunnel junctions integrated with 130 nm CMOS produce tunable fluctuating digital outputs for p-bits.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper shows that superparamagnetic tunnel junctions can be fabricated directly on standard 130 nm CMOS chips to form working p-bit circuits. Resistance fluctuations from thermal noise in the junctions translate into a digital voltage that switches probabilistically and can be adjusted by changing an input voltage. This integration step removes a major barrier to building larger probabilistic computing systems using existing semiconductor processes. A reader would care because it demonstrates a path from laboratory concepts to manufacturable hardware for optimization and machine learning tasks.

Core claim

Experimental results of a p-bit unit cell using sMTJs integrated with 130 nm CMOS technology demonstrate that the sMTJ's resistance fluctuations can generate a corresponding fluctuating digital output voltage which is tunable via the input voltage. These findings establish the feasibility of CMOS-compatible, sMTJ-based probabilistic circuits.

What carries the argument

The p-bit unit cell formed by an sMTJ whose thermal resistance fluctuations are read out through CMOS circuitry to produce a voltage output controlled by an input voltage.

Load-bearing premise

The superparamagnetic properties and thermal fluctuation behavior of the sMTJ survive the CMOS integration process without degradation that would prevent usable probabilistic operation.

What would settle it

An integrated device in which the output voltage shows no fluctuations correlated with sMTJ resistance changes or no response to input voltage tuning would falsify the demonstration.

Figures

Figures reproduced from arXiv: 2604.14446 by Advait Madhavan, Hideo Ohno, Jabez J. McClelland, Ju-Young Yoon, Nuno Cacoilo, Shun Kanai, Shunsuke Fukami, William A. Borders.

Figure 1
Figure 1. Figure 1: a) Layout schematic of test chip with 150 isolated sMTJs, 240 sMTJs in series with an NMOS transistor, and 150 full-stage p-bit circuits. b) Schematic of the cross-sectional structure of the integrated chip. c) cross-sectional scanning transmission electron micrograph of an SMTJ integrated above the CMOS. d) Plan￾view scanning electron micrograph of an sMTJ [PITH_FULL_IMAGE:figures/full_fig_p012_1.png] view at source ↗
read the original abstract

Probabilistic computers offer promising solutions for computationally hard problems in domains such as combinatorial optimization and machine learning. A key building block in these systems is the probabilistic bit (p-bit), which relies on superparamagnetic tunnel junctions (sMTJs) as its source of randomness. A challenging threshold to cross for scaling sMTJ-based p-bit systems is integration of sMTJs with CMOS technology. In this work, we present experimental results of a p-bit unit cell using sMTJs integrated with 130 nm CMOS technology and demonstrate that the sMTJ's resistance fluctuations can generate a corresponding fluctuating digital output voltage which is tunable via the input voltage. These findings establish the feasibility of CMOS-compatible, sMTJ-based probabilistic circuits and mark a key step toward scalable hardware for real-world probabilistic computing applications.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 1 minor

Summary. The paper presents experimental results on a p-bit unit cell fabricated by integrating superparamagnetic tunnel junctions (sMTJs) with 130 nm CMOS technology. It claims to show that the sMTJ resistance fluctuations produce a corresponding fluctuating digital output voltage that can be tuned by varying the input voltage, thereby demonstrating the feasibility of CMOS-compatible sMTJ-based probabilistic circuits.

Significance. If the experimental results are robustly supported by appropriate characterization, this integration represents a meaningful advance toward scalable hardware for probabilistic computing. The work directly addresses the integration barrier between sMTJs and standard CMOS processes, which is a recognized obstacle for practical p-bit implementations in optimization and machine-learning applications.

major comments (1)
  1. [Experimental results section] The central claim of tunable fluctuating digital output arising from sMTJ superparamagnetic behavior (abstract and experimental results section) is not supported by the required controls or statistics. No dwell-time histograms, autocorrelation functions, temperature dependence, or pre- versus post-integration comparisons of fluctuation rates or effective anisotropy are reported, leaving open the possibility that the observed voltage fluctuations originate from circuit noise, interface traps, or fabrication damage rather than thermally activated superparamagnetic switching. This evidence gap is load-bearing for the p-bit feasibility conclusion.
minor comments (1)
  1. [Abstract] The abstract states that the output is 'tunable via the input voltage' but does not specify the quantitative metric (e.g., probability shift per volt or range of bias voltages) used to establish tunability.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for their constructive and detailed review of our manuscript. We have carefully considered the major comment and provide a point-by-point response below, along with revisions to the manuscript where appropriate.

read point-by-point responses

  1. Referee: [Experimental results section] The central claim of tunable fluctuating digital output arising from sMTJ superparamagnetic behavior (abstract and experimental results section) is not supported by the required controls or statistics. No dwell-time histograms, autocorrelation functions, temperature dependence, or pre- versus post-integration comparisons of fluctuation rates or effective anisotropy are reported, leaving open the possibility that the observed voltage fluctuations originate from circuit noise, interface traps, or fabrication damage rather than thermally activated superparamagnetic switching. This evidence gap is load-bearing for the p-bit feasibility conclusion.

    Authors: We agree that additional statistical characterization would strengthen the attribution of the observed fluctuations to sMTJ superparamagnetic switching. The manuscript already shows that the amplitude and character of the digital output fluctuations are tunable by the input voltage applied across the sMTJ, a dependence that is inconsistent with voltage-independent sources such as circuit noise, interface traps, or fabrication-induced damage. Nevertheless, we acknowledge the value of the requested controls. In the revised manuscript we have added dwell-time histograms and autocorrelation functions computed directly from the measured voltage time series; these exhibit the expected exponential dwell-time distributions and correlation times consistent with thermally activated superparamagnetic switching. Temperature dependence and pre- versus post-integration comparisons of fluctuation rates were not performed in the present study. We have expanded the experimental results and discussion sections to explain that all measurements were conducted at room temperature, to reference prior literature on sMTJ temperature scaling, and to note that post-integration electrical characterization confirms the persistence of the expected fluctuating behavior. These additions address the evidence gap while preserving the focus on CMOS integration. revision: partial

Circularity Check

0 steps flagged

No circularity; purely experimental demonstration with no derivation chain or fitted predictions.

full rationale

The manuscript reports experimental integration of sMTJs with 130 nm CMOS and direct observation of resistance fluctuations producing tunable digital voltage outputs. No equations, first-principles derivations, parameter fitting, or predictions are presented; the feasibility claim rests entirely on measured device behavior. No self-citations, ansatzes, or uniqueness theorems are invoked to support any mathematical step, and the skeptic concern about confirming superparamagnetic origin is an empirical validation issue rather than a circularity in derivation. The paper is self-contained against external benchmarks via its reported measurements.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The work is an experimental demonstration relying on established device physics of sMTJs and CMOS; no new free parameters, invented entities, or ad-hoc axioms are introduced beyond standard assumptions about thermal fluctuations in superparamagnetic devices.

axioms (1)
  • domain assumption Superparamagnetic tunnel junctions exhibit thermally driven resistance fluctuations suitable for generating probabilistic signals when integrated with CMOS.
    This underpins the p-bit operation and is invoked implicitly in the abstract's description of fluctuations generating digital output.

pith-pipeline@v0.9.0 · 5462 in / 1185 out tokens · 53321 ms · 2026-05-10T11:14:04.573550+00:00 · methodology

discussion (0)

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Reference graph

Works this paper leans on

18 extracted references · 18 canonical work pages

  1. [1]

    K. Y. Camsari, R. Faria, B. M. Sutton, and S. Datta, Stochastic p-Bits for Invertible Logic, Phys. Rev. X, vol. 7, no. 3, 031014, Jul. 2017, doi: 10.1103/PhysRevX.7.031014

    work page doi:10.1103/physrevx.7.031014 2017

  2. [2]

    Lucas, Ising formulations of many np problems, Frontiers in Physics2, 10.3389/fphy.2014.00005 (2014)

    A. Lucas, Ising formulations of many NP problems, Front. Phys. vol. 2, no. 5, Feb. 2014, doi: https://doi.org/10.3389/fphy.2014.00005

    work page doi:10.3389/fphy.2014.00005 2014

  3. [3]

    N. A. Aadit, A. Grimaldi, M. Carpentieri, L. Theogarajan, J. M. Martinis, G. Finocchio, and K. Y. Camsari, Massively parallel probabilistic computing with sparse Ising machines, Nat. Electronics, vol. 5, pp. 460-468, Jun. 2022, doi: https://doi.org/10.1038/s41928-022-00774-2

    work page doi:10.1038/s41928-022-00774-2 2022

  4. [4]

    Delacour, M

    C. Delacour, M. M. H. Sajeeb, J. P. Hespanha, and K. Y. Camsari, Two- dimensional parallel tempering for constrained optimization, Phys. Rev. E, vol. 112, no. 2, pp. L023301, Aug. 2025, doi: 10.1103/mr2n-qqrb

    work page doi:10.1103/mr2n-qqrb 2025

  5. [5]

    M. M. H. Sajeeb, N. A. Aadit, S Chowdhury, T. Wu, S. Smith, D. Chinmay, A. Raut, K. Y. Camsari, C. Delacour, T. Srimani, Scalable connectivity for Ising machines: Dense to sparse, Phys. Rev. Appl., vol. 24, pp. 014005, Jul. 2025, doi: https://doi.org/10.1103/kx8m-5h3h

    work page doi:10.1103/kx8m-5h3h 2025

  6. [6]

    Julliere, Tunneling between ferromagnetic films, Phys

    M. Julliere, Tunneling between ferromagnetic films, Phys. Lett. A, vol. 54, pp. 225-226, Jun. 1975, doi: https://doi.org/10.1016/0375-9601(75)901747

    work page doi:10.1016/0375-9601(75)901747 1975

  7. [7]

    A. D. Kent and D. C. Worledge, A new spin on magnetic memories, Nature Nanotechnology, vol. 10, no. 187, Mar. 2015, doi: 10.1038/nnano.2015.24

    work page doi:10.1038/nnano.2015.24 2015

  8. [8]

    Bhatti, R

    S. Bhatti, R. Sbiaa, A. Hirohata, H. Ohno, S. Fukami, S. N. Piramanayagam, Spintronics based random access memory: a review, Materials Today, vol. 20, pp. 530-548, Sept. 2017, doi: https://doi.org/10.1016/j.mattod.2017.07.007

    work page doi:10.1016/j.mattod.2017.07.007 2017

  9. [9]

    Hayakawa, S

    K. Hayakawa, S. Kanai, T. Funatsu, J. Igarashi, B. Jinnai, W. A. Borders, H. Ohno, and S. Fukami, Nanosecond Random Telegraph Noise in InPlane Magnetic Tunnel Junctions, Phys. Rev. Lett., vol. 126, pp. 117202, Mar. 2021, doi: https://doi.org/10.1103/PhysRevLett.126.117202

    work page doi:10.1103/physrevlett.126.117202 2021

  10. [10]

    Safranski, J

    C. Safranski, J. Kaiser, P. Trouilloud, P. Hashemi, G. Hu, and J. Z. Sun, Demonstration of Nanosecond Operation in Stochastic Magnetic Tunnel Junctions, Nano Letters, vol. 21, no. 5, pp. 2040-2045, Feb. 2021, doi: https://doi.org/10.1021/acs.nanolett.0c04652

    work page doi:10.1021/acs.nanolett.0c04652 2040

  11. [11]

    W. A. Borders, A. Z. Pervaiz, K. Y. Camsari, S. Fukami, H. Ohno, and S. Datta, Integer factorization using stochastic magnetic tunnel junctions, Nature, vol. 573, pp. 390-393, Sept. 2019, doi: https://doi.org/10.1038/s41586-019-1557-9

    work page doi:10.1038/s41586-019-1557-9 2019

  12. [12]

    Kaiser, W

    J. Kaiser, W. A. Borders, K. Y Camsari, S. Fukami, H. Ohno, and S. Datta, Hardware-Aware In Situ Learning Based on Stochastic Magnetic Tunnel Junctions, Phys. Rev. Appl. vol. 17, pp. 014016, Jan. 2022, doi: 10.1103/PhysRevApplied.17.014016

    work page doi:10.1103/physrevapplied.17.014016 2022

  13. [13]

    Characterizing and Modelling of the BTI Reliability in IGZO-TFT using Light-assisted I-V Spectroscopy,

    A. Grimaldi, K. Selcuk, N. A. Aadit, K. Kobayashi, Q. Cao, S.Chowdhury, G. Finocchio, S. Kanai, H. Ohno, S. Fukami, K. Y. Camsari Experimental evaluation of simulated quantum annealing with MTJ-augmented p-bits 2022 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2022, pp. 1-4, doi: 10.1109/IEDM45625.2022.10019530

    work page doi:10.1109/iedm45625.2022.10019530 2022

  14. [14]

    N. S. Singh, K. Kobayashi, Q. Cao, K. Selcuk, T. Hu, S. Niazi, N. A. Aadit, S. Kanai, H. Ohno, S. Fukami, and K. Y. Camsari, CMOS plus stochastic nanomagnets enabling heterogeneous computers for probabilistic inference and learning, Nature Communications, vol. 15, no. 2685, Nar. 2024, doi: https://doi.org/10.1038/s41467-024-466456

    work page doi:10.1038/s41467-024-466456 2024

  15. [15]

    J. Si, S. Yang, Y. Cen, S. Chen, Y. Huang, Z. Yao, G.-J. Kim, K. Cai, J. Yoo, X. Fong, and H. Yang, Energy-efficient superparamagnetic Ising machine and its application to traveling salesman problems, Nature Communications, vol. 15, no. 3457, Apr 2024, doi: https://doi.org/10.1038/s41467-024-47818-z

    work page doi:10.1038/s41467-024-47818-z 2024

  16. [16]

    M. A. Iftakher, H. Levices, K.-E. Harabi, A. Renaudineau, M.-C. Faye, C. Bouchard, F. Disdier, B. Viala, E. Vianello, P. Talatchian, K. Garello, D. Querlioz, and L. Hutin, Intrinsic Annealing in a Hybrid Memristor-Magnetic Tunnel Junction Ising Machine, arXiv:2506.14676, doi: https://doi.org/10.48550/arXiv.2506.14676

    work page doi:10.48550/arxiv.2506.14676

  17. [17]

    K. Y. Camsari, S. Salahuddin, and S. Datta, Implementing p-bits With Embedded MTJ, IEEE EDL, vol. 38, no. 12, pp. 1767-1770, Dec. 2017, doi: 10.1109/LED.2017.2768321

    work page doi:10.1109/led.2017.2768321 2017

  18. [18]

    Jenkins, A

    S. Jenkins, A. Meo, L. E. Elliott, S. K. Piotrowski, M. Bapna, R. W. Chantrell, S. A. Majetich, and R. H. L. Evans, Magnetic stray fields in nanoscale magnetic tunnel junctions, Jour. of Phys. D, vol. 53, pp. 044001, doi: 10.1088/1361-6463/ab4fbf. Figures Fig. 1. a) Layout schematic of test chip with 150 isolated sMTJs, 240 sMTJs in series with an NMOS tr...

    work page doi:10.1088/1361-6463/ab4fbf