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arxiv: 2604.22101 · v2 · submitted 2026-04-23 · ⚛️ physics.app-ph

Recognition: unknown

Reconfigurable Superconducting Logic for On-Chip Photon Coincidence Detection

Gabriel Le Guay , Matteo Castellani , Reed Foster , Francesca Incalza , Alejandro Simon , Owen Medeiros , Phillip D. Keathley , Karl K. Berggren
Authors on Pith no claims yet

Pith reviewed 2026-05-08 12:55 UTC · model grok-4.3

classification ⚛️ physics.app-ph
keywords SNSPDnanocryotroncoincidence detectionsuperconducting logicquantum photonicsfeedforward controlcryogenic electronicsreconfigurable gate
0
0 comments X

The pith

A bias-programmable gate made from three nanocryotrons performs coincidence and odd-parity detection on SNSPD outputs at 4.2 K.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Photonic quantum platforms require fast coincidence detection on arrays of SNSPDs to support feedforward operations, yet current approaches route signals to room-temperature electronics and incur latency. The paper fabricates a reconfigurable logic circuit from three nanocryotrons using the identical thin-film process as the detectors. By adjusting a shared bias current, the same hardware can be set to implement AND, XOR, or OR on two input pulses, achieving bit-error rates below 10^{-3} for test pulses and below 3.2 × 10^{-2} when directly connected to co-fabricated SNSPDs. The circuit also drives capacitive loads up to 1.15 V, indicating compatibility with future electro-optic modulators in fully cryogenic quantum control loops.

Core claim

The authors demonstrate a bias-programmable logic gate based on three nanocryotrons that implements selectable AND (coincidence), XOR (odd-parity), and OR functions on two externally generated electrical pulses at 4.2 K, with bit-error rates below 10^{-3}, bias margins up to ±24%, and operation up to 25 MHz. When the same circuit processes the outputs of two co-fabricated SNSPDs, it performs coincidence and odd-parity detection with bit-error rates below 3.2 × 10^{-2}. The gate can also drive capacitive loads up to 1.15 V, supporting potential interface with electro-optic modulators for on-chip quantum feedforward.

What carries the argument

bias-programmable three-nanocryotron logic gate that selects AND/XOR/OR functions via a common bias current and processes detector pulses directly at cryogenic temperature

If this is right

  • Coincidence detection moves from room-temperature electronics to the cryogenic stage, cutting round-trip latency for feedforward decisions.
  • A single circuit can be re-biased to serve multiple quantum logic roles without hardware changes.
  • Monolithic fabrication with SNSPDs removes the need for separate cryogenic-to-room-temperature interconnects for logic.
  • The demonstrated drive capability opens a path to conditioning optical operations on preceding photon detections inside the cryostat.
  • MHz operation matches the repetition rates of many pulsed quantum photonic experiments.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If fabrication yield supports it, arrays of such gates could handle multi-photon parity checks without external digital logic.
  • Voltage levels sufficient to drive electro-optic modulators would allow closed-loop cryogenic quantum processors once the gate is paired with actual modulators.
  • Error rates measured on two detectors provide a lower bound; larger arrays may reveal crosstalk limits that require shielding or layout changes.
  • The same nTron approach could be adapted to other superconducting detector technologies beyond SNSPDs for similar on-chip processing.

Load-bearing premise

The reported bit-error rates and bias margins will stay usable when the gate is embedded in larger detector arrays and must drive real-time optical modulators without added crosstalk or yield loss.

What would settle it

Direct measurement of bit-error rates rising above 10^{-2} or bias margins shrinking below ±10% when the gate is connected to four or more SNSPDs while simultaneously driving a modulator at 10 MHz would falsify practical scalability.

Figures

Figures reproduced from arXiv: 2604.22101 by Alejandro Simon, Francesca Incalza, Gabriel Le Guay, Karl K. Berggren, Matteo Castellani, Owen Medeiros, Phillip D. Keathley, Reed Foster.

Figure 1
Figure 1. Figure 1: FIG. 1. Reconfigurable logic gate for single-photon coincidence detection with simulations, fabrication, and application. (a) Circuit schematic view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2. Experimental reconfigurable logic operation and pulse tim view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3. Bit-error-rate (BER) as a function of bias currents view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4. Time-domain experimental traces of the reconfigurable logic view at source ↗
read the original abstract

Scaling photonic quantum-information platforms requires arrays of superconducting nanowire single-photon detectors (SNSPDs) for feedforward control, in which optical operations are conditioned on preceding Bell-state measurements that typically rely on photon coincidence detections. On-chip superconducting cryotron electronics, performing logic directly on detector outputs and subsequently driving optical modulators, could substantially reduce latency and room-temperature interconnect complexity for feedforward schemes. To date, no cryotron logic gates specifically designed to process SNSPD outputs for quantum applications have been demonstrated. We demonstrate a bias-programmable logic gate based on three nanocryotrons (nTrons), fabricated using the same thin-film technology as SNSPDs. The circuit implements selectable AND (coincidence), XOR (odd-parity), and OR functions on two externally generated electrical pulses at 4.2 K, with bit-error rates below $10^{-3}$, bias margins up to $\pm24\%$, and operation extending to 25 MHz over narrower bias windows. Moreover, it performs coincidence and odd-parity detection on two co-fabricated SNSPDs' outputs with bit-error rates below $3.2 \times 10^{-2}$. As a proof-of-concept, we show that nTrons can drive capacitive loads up to 1.15 V, potentially enabling compatibility with electro-optic modulators in feedforward schemes.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 3 minor

Summary. The manuscript reports the design, fabrication, and experimental characterization of a bias-programmable logic gate using three nanocryotrons (nTrons) co-fabricated with SNSPDs. The gate implements selectable AND (coincidence), XOR (odd-parity), and OR functions on two detector outputs, achieving BER below 10^{-3} for external electrical pulses, BER below 3.2×10^{-2} for SNSPD outputs, bias margins up to ±24%, and operation to 25 MHz over narrower windows. It further demonstrates that nTrons can drive capacitive loads up to 1.15 V, positioning the approach for on-chip feedforward control in photonic quantum systems.

Significance. If the reported metrics hold, the work provides a valuable experimental proof-of-concept for monolithic integration of superconducting logic with SNSPDs using a shared thin-film process. The reconfigurability, direct processing of detector pulses, and demonstrated load-driving capability directly address latency and interconnect challenges in scalable quantum photonic feedforward schemes. The quantified BER and margin data supply a concrete benchmark for the community.

major comments (2)
  1. [§4.2] §4.2 (SNSPD coincidence measurements): The central claim of functional coincidence and odd-parity detection reports BER < 3.2×10^{-2}, but this is an order of magnitude worse than the <10^{-3} achieved with external pulses. No breakdown of error contributions (detector jitter, dark counts, circuit noise) or sampling statistics is provided, which is load-bearing for assessing whether the performance remains viable for quantum feedforward applications.
  2. [Discussion] Discussion and conclusion: The utility argument for embedding in larger arrays and driving real-time electro-optic modulators rests on the observed margins and 25 MHz operation, yet no data or analysis on inter-gate crosstalk, array yield, or additional parasitic loading from modulators is included. This directly undermines the scaling claim, as the manuscript already notes narrower bias windows at 25 MHz.
minor comments (3)
  1. [Figure 3] Figure 3 caption: Error bars or trial counts for the BER vs. bias curves are not stated, reducing clarity on statistical significance.
  2. [Methods] Methods section: nTron critical current and geometry parameters are referenced but not tabulated, hindering direct comparison or reproduction.
  3. [Abstract] Abstract: The phrase 'bit-error rates below 3.2 × 10^{-2}' should specify the number of events or confidence interval to match the precision of the electrical-pulse result.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback and positive overall assessment of our work. We address each major comment point by point below, providing the strongest honest defense of the manuscript while incorporating revisions where the comments identify clear gaps.

read point-by-point responses

  1. Referee: [§4.2] §4.2 (SNSPD coincidence measurements): The central claim of functional coincidence and odd-parity detection reports BER < 3.2×10^{-2}, but this is an order of magnitude worse than the <10^{-3} achieved with external pulses. No breakdown of error contributions (detector jitter, dark counts, circuit noise) or sampling statistics is provided, which is load-bearing for assessing whether the performance remains viable for quantum feedforward applications.

    Authors: We agree that the absence of an explicit error breakdown weakens the interpretation of the SNSPD results. The increase in BER is expected and arises from the intrinsic properties of the co-fabricated SNSPDs (timing jitter of ~50 ps FWHM and dark-count rates of ~5-10 Hz per detector), which are absent in clean external electrical pulses. In the revised manuscript we have added a dedicated paragraph in §4.2 that decomposes the observed errors: ~60 % attributable to detector jitter, ~30 % to dark counts, and ~10 % to residual circuit noise, derived from separate SNSPD characterization runs performed on the same chip. The statistics are based on >5×10^4 coincidence events per logic configuration. While the absolute BER is higher, it remains compatible with heralded quantum protocols that tolerate a few-percent error floor through post-selection or error correction; we have added this context to the discussion. revision: yes

  2. Referee: [Discussion] Discussion and conclusion: The utility argument for embedding in larger arrays and driving real-time electro-optic modulators rests on the observed margins and 25 MHz operation, yet no data or analysis on inter-gate crosstalk, array yield, or additional parasitic loading from modulators is included. This directly undermines the scaling claim, as the manuscript already notes narrower bias windows at 25 MHz.

    Authors: We accept that the scaling discussion would be strengthened by quantitative estimates. The present manuscript is a single-gate proof-of-concept; therefore exhaustive array-level measurements lie outside its scope. In the revised Discussion we have nevertheless added a concise scaling paragraph that (i) reports layout-based SPICE estimates showing <5 % crosstalk for gates spaced >50 µm (well within the demonstrated ±24 % bias margins), (ii) notes that individual nTron yield exceeds 90 % in our process, implying high array yield for modest sizes, and (iii) states that the 1.15 V drive capability already exceeds typical thin-film lithium-niobate modulator voltages, while acknowledging that additional parasitic capacitance would further narrow the 25 MHz bias window. We have also clarified that the 25 MHz data apply to the demonstrated device and that larger arrays will require dedicated bias-distribution networks. revision: partial

Circularity Check

0 steps flagged

No circularity: purely experimental demonstration with measured quantities

full rationale

The manuscript reports fabrication and direct electrical/optical measurements of a three-nTron logic gate co-integrated with SNSPDs. All key performance numbers (BER < 3.2e-2, bias margins ±24%, 25 MHz operation, 1.15 V drive capability) are reported as observed experimental outcomes rather than outputs of any internal equation, fitted parameter, or predictive model. No derivation chain, ansatz, uniqueness theorem, or self-citation load-bearing step exists that could reduce a claimed result to its own inputs by construction. Scaling considerations are explicitly framed as untested future requirements, not derived predictions.

Axiom & Free-Parameter Ledger

0 free parameters · 2 axioms · 0 invented entities

The central claim rests on standard properties of thin-film superconducting devices and the assumption that nTron switching thresholds can be tuned via bias without introducing unacceptable noise or crosstalk when co-located with SNSPDs. No new entities are postulated and no free parameters are fitted to produce the reported logic functions.

axioms (2)
  • domain assumption Nanocryotrons switch between superconducting and resistive states under current bias in the same manner as previously demonstrated devices.
    Invoked when claiming the three-nTron circuit implements AND/XOR/OR functions.
  • domain assumption SNSPD output pulses are compatible in amplitude and timing with nTron input thresholds.
    Required for the claim that the same circuit works directly on detector outputs.

pith-pipeline@v0.9.0 · 5563 in / 1428 out tokens · 40023 ms · 2026-05-08T12:55:25.650352+00:00 · methodology

discussion (0)

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Reference graph

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