Pith. sign in

REVIEW 3 major objections 1 minor 36 references

FlowPlace: Flow Matching for Chip Placement

T0 review · 3 major / 1 minor · reviewed 2026-07-01 · grok-4.3

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗

Pith's one-line read FlowPlace replaces diffusion models with flow matching for chip placement to deliver better PPA, 10-50 times faster sampling, and zero overlaps.

desk verdict FlowPlace swaps diffusion for flow matching plus mask-guided data and hard constraints to target sampling speed and overlaps in chip placement, but the abstract supplies no mechanism or experimental details to back the claims. read the letter →

arxiv 2604.23658 v2 pith:UAP4XNP5 submitted 2026-04-26 cs.AR cs.AIcs.LG

Peng Xie , Ke Xue , Yunqi Shi , Ruo-Tong Chen , Chengrui Gao , Siyuan Xu , Chenjian Ding , Mingxuan Yuan
show 1 more author
Chao Qian
This is my paper · ORCID
classification cs.ARcs.AIcs.LG
keywords chipplacementflowmatchinggenerativemodelsphysicaldesignoverlap-freelayoutsPPAoptimizationsyntheticdatahardconstraints
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper argues that existing generative approaches to chip placement suffer from slow sampling and overlaps because they rely on random synthetic data and gradient-based solvers. FlowPlace counters this by generating mask-guided synthetic data, training a flow model with flexible prior injection, and enforcing hard constraints during sampling. If these changes work as described, placement becomes both faster and reliably overlap-free while still improving power, performance, and area on standard benchmarks. A sympathetic reader would care because faster, cleaner placement directly shortens the physical-design loop in chip development.

What carries the argument

Flow matching with mask-guided synthetic data and hard constraint sampling: the flow model learns a direct mapping from noise to valid layouts while the constraints eliminate overlaps at sampling time.

What would settle it

Testing FlowPlace on a new, held-out real-world design and finding either overlaps or worse PPA than the diffusion baseline would falsify the central claim.

Watch

Extended reading notes

Core claim

FlowPlace shows that flow matching, when paired with mask-guided synthetic data generation and hard constraint sampling, produces overlap-free chip layouts that improve PPA metrics and sample 10-50 times faster than diffusion-based baselines on OpenROAD and ICCAD 2015 benchmarks.

Load-bearing premise

Mask-guided synthetic data plus hard constraint sampling will produce layouts that generalize to real designs and keep the reported PPA gains without hidden trade-offs.

Editorial extensions

If this is right

  • Chip placement can be performed with zero overlaps without post-processing fixes.
  • Sampling time drops by a factor of 10-50 compared with diffusion models.
  • PPA metrics improve on both OpenROAD and ICCAD 2015 benchmark suites.
  • Flexible prior injection allows the same trained model to accommodate different design constraints.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The same flow-matching recipe could be tested on other physical-design stages such as routing or floorplanning.
  • If the hard constraints prove robust, the method might reduce reliance on iterative legalization steps in commercial tools.
  • Faster sampling opens the possibility of using placement inside larger search loops that explore multiple candidate floorplans.
Share X Bluesky LinkedIn Reddit HN

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

3 major / 1 minor

Summary. The manuscript proposes FlowPlace, a flow-matching generative model for chip placement. It claims to overcome diffusion-model limitations via mask-guided synthetic data generation, flow-based training with flexible prior injection, and hard-constraint sampling that yields strictly overlap-free layouts. Experiments on OpenROAD and ICCAD 2015 benchmarks are said to demonstrate improved PPA metrics, 10-50× faster sampling than diffusion baselines, and zero overlaps.

Significance. If the central claims are substantiated with detailed mechanisms and reproducible experiments, the work could advance learning-based physical design by demonstrating an efficient, constraint-aware generative approach that avoids the sampling-time and overlap issues of prior diffusion methods. The emphasis on flow matching for speed is a potentially useful direction for EDA applications.

major comments (3)
  1. [Abstract] Abstract: performance claims (better PPA, 10-50× faster sampling, zero overlaps) are asserted without any mention of baselines, statistical tests, ablation studies, or experimental protocol, so the data cannot be verified to support the claims.
  2. [Method] Method description: the hard-constraint sampling procedure is stated only at the level of “hard constraint sampling for overlap-free layouts” with no equation, algorithm, or description of how the constraint is injected into the flow ODE (vector-field modification, projection, or separate solver). This mechanism is load-bearing for both the zero-overlap guarantee and the claimed PPA gains on tightly coupled netlists.
  3. [Experiments] Experiments / generalization: no details are supplied on how mask-guided synthetic pre-training matches the distribution of the ICCAD/OpenROAD benchmarks or on any held-out testing that would confirm the PPA improvements are not due to benchmark-specific tuning or hidden quality trade-offs.
minor comments (1)
  1. [Abstract] Abstract: the phrase “flexible prior injection” is introduced without any elaboration on its implementation or difference from standard flow-matching priors.

Simulated Author's Rebuttal

3 responses · 0 unresolved

We thank the referee for the detailed and constructive review. We address each major comment below, indicating revisions that will strengthen the manuscript. All requested clarifications can be incorporated in a revised version.

read point-by-point responses

  1. Referee: [Abstract] Abstract: performance claims (better PPA, 10-50× faster sampling, zero overlaps) are asserted without any mention of baselines, statistical tests, ablation studies, or experimental protocol, so the data cannot be verified to support the claims.

    Authors: We agree the abstract is too concise. In the revision we will expand it to explicitly name the diffusion baselines, state that results are averaged over multiple random seeds with reported standard deviations, and note the benchmark sets (OpenROAD and ICCAD 2015) together with the evaluation protocol. This will make the performance claims verifiable from the abstract alone. revision: yes

  2. Referee: [Method] Method description: the hard-constraint sampling procedure is stated only at the level of “hard constraint sampling for overlap-free layouts” with no equation, algorithm, or description of how the constraint is injected into the flow ODE (vector-field modification, projection, or separate solver). This mechanism is load-bearing for both the zero-overlap guarantee and the claimed PPA gains on tightly coupled netlists.

    Authors: The referee is correct that the current description is insufficient. We will add a dedicated subsection (approximately one page) that supplies the precise ODE modification: the vector field is projected onto the feasible set at each integration step via a differentiable overlap penalty that is zero inside the feasible region. The algorithm box and the corresponding mathematical derivation will be included so that the zero-overlap guarantee and its effect on PPA can be reproduced. revision: yes

  3. Referee: [Experiments] Experiments / generalization: no details are supplied on how mask-guided synthetic pre-training matches the distribution of the ICCAD/OpenROAD benchmarks or on any held-out testing that would confirm the PPA improvements are not due to benchmark-specific tuning or hidden quality trade-offs.

    Authors: We acknowledge the gap. The revision will include (i) quantitative distribution statistics (macro-size histograms, net-degree distributions) comparing the mask-guided synthetic corpus to the target benchmarks, (ii) an explicit statement of the train/validation/test split used for the ICCAD 2015 and OpenROAD suites, and (iii) an ablation that isolates the contribution of the mask-guided pre-training versus training from scratch. These additions will demonstrate that the reported gains are not the result of hidden overfitting. revision: yes

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity detected in derivation chain

full rationale

The provided abstract and description contain no equations, derivations, fitted parameters, or self-citations that could reduce claims to inputs by construction. Claims rest on empirical benchmark results (OpenROAD, ICCAD 2015) for PPA, speed, and zero overlaps, which are externally falsifiable rather than self-referential. No load-bearing steps match any enumerated circularity pattern; the method description is self-contained against external benchmarks with no mathematical chain to inspect for equivalence to inputs.

Assumptions & free parameters 0 free parameters · 0 assumptions · 0 invented entities

Abstract-only review supplies no identifiable free parameters, axioms, or invented entities; full manuscript required for ledger construction.

how reviews work

0 comments
Cite this review

Pith. "Pith review of FlowPlace: Flow Matching for Chip Placement." pith.science (2026). https://pith.science/paper/UAP4XNP5

@misc{pith2026260423658,
  author       = {Pith},
  title        = {Pith review of: FlowPlace: Flow Matching for Chip Placement},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/UAP4XNP5}},
  note         = {Machine review of arXiv:2604.23658}
}
abstract

Chip placement plays an important role in physical design. While generative models like diffusion models offer promising learning-based solutions, current methods have the following limitations: they use random synthetic data for pre-training, require long sampling times, and often result in overlaps due to their dependence on gradient-based solvers during the sampling process. To overcome these issues, we propose FlowPlace, which features mask-guided synthetic data generation, flow-based efficient training with flexible prior injection, and hard constraint sampling for overlap-free layouts. Experiments on OpenROAD and ICCAD 2015 benchmarks show FlowPlace achieves better PPA metrics, 10-50$\times$ faster sampling efficiency, and zero overlaps.

Figures

Figures reproduced from arXiv: 2604.23658 by the authors.

Figure 1
Figure 1. Comparison of placement performance on su￾perblue7. EfficientPlace (RL-based) places macros sequen￾tially, while ChipDiffusion and FlowPlace (generative model￾based) simultaneously move all macro positions. FlowPlace demonstrates superior performance with the lowest HPWL and zero overlap. Their sequential decision-making nature also creates a bot￾tleneck, as early suboptimal choices have irreversible and compounding… view at source ↗
Figure 2
Figure 2. Progressive constraint enforcement process of hard constraint guided sampling. For clarity, we only show one movable macro 𝐴. 20-50 steps, compared to the requirement of 1000 steps in ChipDiffusion [17]. 3.3 Hard Constraint Guided Sampling While the learned flow model generates placements effi￾ciently, it does not inherently guarantee hard constraints such as non-overlap. ChipDiffusion [17] addresses this via gradie… view at source ↗
Figure 3
Figure 3. Placement layouts and congestion visualization on superblue1. Red points are the congestion critical regions. These results underscore FlowPlace’s generalization capabil￾ity and practical value in realistic design settings. 4.2 Additional Results Visualization Analysis view at source ↗

Review history (2 revisions) →

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

36 extracted references · 36 canonical work pages

  1. [1]

    Anthony Agnesina, Puranjay Rajvanshi, Tian Yang, Geraldo Pradipta, Austin Jiao, Ben Keller, Brucek Khailany, and Haoxing Ren. 2023. Au- toDMP: Automated DREAMPlace-based macro placement. InProceed- ings of the 2023 International Symposium on Physical Design

    work page 2023

  2. [2]

    Tutu Ajayi, Vidya A Chhabria, Mateus Fogaça, Soheil Hashemi, Abdel- rahman Hosny, Andrew B Kahng, Minsoo Kim, Jeongsup Lee, Uday Mallappa, Marina Neseem, et al. 2019. Toward an open-source digital flow: First learnings from the openroad project. InProceedings of the 56th Design Automation Conference

    work page 2019

  3. [3]

    Shaked Brody, Uri Alon, and Eran Yahav. 2022. How attentive are graph attention networks?. InProceedings of the 10th International Conference on Learning Representations

    work page 2022

  4. [4]

    Yifan Chen, Zaiwen Wen, Yun Liang, and Yibo Lin. 2023. Stronger mixed-size placement backbone considering second-order information. InProceedings of the 42nd International Conference on Computer Aided Design

    work page 2023

  5. [5]

    Maddix, Abdul Fatir Ansari, Andrew Stuart, Michael W

    Chaoran Cheng, Boran Han, Danielle C. Maddix, Abdul Fatir Ansari, Andrew Stuart, Michael W. Mahoney, and Bernie Wang. 2025. Gradient- free generation for hard-constrained systems. InProceedings of the 13th International Conference on Learning Representations

    work page 2025

  6. [6]

    Chung-Kuan Cheng, Andrew B Kahng, Ilgweon Kang, and Lutong Wang. 2018. Replace: Advancing solution quality and routability validation in global placement.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems38, 9 (2018), 1717–1730

    work page 2018

  7. [7]

    Chung-Kuan Cheng, Andrew B Kahng, Sayak Kundu, Yucheng Wang, and Zhiang Wang. 2023. Assessment of reinforcement learning for macro placement. InProceedings of the 2023 International Symposium on Physical Design

    work page 2023

  8. [8]

    Ruoyu Cheng and Junchi Yan. 2021. On joint learning for solving place- ment and routing in chip design. InAdvances in Neural Information Processing Systems 34

    work page 2021

Show all 36 references
  1. [9]

    Zijie Geng, Jie Wang, Ziyan Liu, Siyuan Xu, Zhentao Tang, Mingxuan Yuan, Jianye Hao, Yongdong Zhang, and Feng Wu. 2024. Reinforcement learning within tree search for fast macro placement. InProceedings of the 41st International Conference on Machine Learning

    2024

  2. [10]

    Anna Goldie, Azalia Mirhoseini, and Jeff Dean. 2024. That chip has sailed: A critique of unfounded skepticism around AI for chip design. arxiv:2411.10053(2024)

    2024

  3. [11]

    Jonathan Ho, Ajay Jain, and Pieter Abbeel. 2020. Denoising diffusion probabilistic models. InAdvances in Neural Information Processing Systems 33

    2020

  4. [12]

    Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, and Jun Gu. 2000. Corner block list: An effective and efficient topological representation of non-slicing floorplan. In Proceedings of the 13th International Conference on Computer Aided Design

    2000

  5. [13]

    Andrew B Kahng, Ravi Varadarajan, and Zhiang Wang. 2023. Hier- RTLMP: A hierarchical automatic macro placer for large-scale complex IP blocks.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems43, 5 (2023)

    2023

  6. [14]

    Myung-Chul Kim, Jin Hu, Jiajia Li, and Natarajan Viswanathan. 2015. ICCAD-2015 CAD contest in incremental timing-driven placement and benchmark suite. InProceedings of the 34th International Conference on Computer-Aided Design

    2015

  7. [15]

    Yao Lai, Jinxin Liu, Zhentao Tang, Bin Wang, Jianye Hao, and Ping Luo

  8. [16]

    InProceedings of the 40th International Conference on Machine Learning

    ChiPFormer: Transferable chip placement via offline decision transformer. InProceedings of the 40th International Conference on Machine Learning

  9. [17]

    Yao Lai, Yao Mu, and Ping Luo. 2022. MaskPlace: Fast chip placement via reinforced visual representation learning. InAdvances in Neural Information Processing Systems 35

    2022

  10. [18]

    Vint Lee, Minh Nguyen, Leena Elzeiny, Chun Deng, Pieter Abbeel, and John Wawrzynek. 2025. Chip placement with diffusion models. In Proceedings of the 42nd International Conference on Machine Learning

    2025

  11. [19]

    Peiyu Liao, Dawei Guo, Zizheng Guo, Siting Liu, Yibo Lin, and Bei Yu

  12. [20]

    DREAMPlace 4.0: Timing-driven placement with momentum- based net weighting and lagrangian-based refinement.IEEE Transac- tions on Computer-Aided Design of Integrated Circuits and Systems42, 10 (2023), 3374–3387

    2023

  13. [21]

    Jai-Ming Lin, Szu-Ting Li, and Yi-Ting Wang. 2019. Routability-driven mixed-size placement prototyping approach considering design hier- archy and indirect connectivity between macros. InProceedings of the 56th Design Automation Conference

    2019

  14. [22]

    Yibo Lin, Zixuan Jiang, Jiaqi Gu, Wuxi Li, Shounak Dhar, Haoxing Ren, Brucek Khailany, and David Z Pan. 2020. DREAMPlace: Deep learning toolkit-enabled gpu acceleration for modern VLSI placement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems40, ...

    2020

  15. [23]

    Yaron Lipman, Ricky TQ Chen, Heli Ben-Hamu, Maximilian Nickel, and Matt Le. 2023. Flow matching for generative modeling. InProceed- ings of the 11th International Conference on Learning Representations

    2023

  16. [24]

    Xingchao Liu, Chengyue Gong, and Qiang Liu. 2022. Flow straight and fast: Learning to generate and transfer data with rectified flow. In Proceedings of the 10th International Conference on Learning Represen- tations

    2022

  17. [25]

    Azalia Mirhoseini, Anna Goldie, Mustafa Yazgan, Joe Wenjie Jiang, Ebrahim Songhori, Shen Wang, Young-Joon Lee, Eric Johnson, Omkar Pathak, Azade Nazi, et al. 2021. A graph placement methodology for fast chip design.Nature594, 7862 (2021), 207–212

    2021

  18. [26]

    Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, and Yoji Kajitani. 1996. VLSI module placement based on rectangle-packing by the sequence-pair.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems15, 12 (1996), 1518–1524

    1996

  19. [27]

    John K Ousterhout. 1984. Corner stitching: A data-structuring tech- nique for VLSI layout tools.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems3, 1 (1984), 87–100

    1984

  20. [28]

    Yuan Pu, Tinghuan Chen, Zhuolun He, Chen Bai, Haisheng Zheng, Yibo Lin, and Bei Yu. 2024. IncreMacro: Incremental macro placement refinement. InProceedings of the 2024 International Symposium on Physical Design

    2024

  21. [29]

    Yunqi Shi, Xi Lin, Siyuan Xu, Shixiong Kai, Ke Xue, Mingxuan Yuan, Chao Qian, and Zhi-Hua Zhou. 2025. ReMaP: Macro placement by re- cursively prototyping and periphery-guided relocating. InProceedings of the 62nd Design Automation Conference

    2025

  22. [30]

    Yunqi Shi, Ke Xue, Lei Song, and Chao Qian. 2023. Macro placement by wire-mask-guided black-box optimization. InAdvances in Neural Information Processing Systems 36

    2023

  23. [31]

    Alexander Tong, Kilian Fatras, Nikolay Malkin, Guillaume Huguet, Yanlei Zhang, Jarrid Rector-Brooks, Guy Wolf, and Yoshua Bengio

  24. [32]

    Improving and generalizing flow-based generative models with minibatch optimal transport.Transactions on Machine Learning Re- search(2024), 1–34

    2024

  25. [33]

    Gomez, Łukasz Kaiser, and Illia Polosukhin

    Ashish Vaswani, Noam Shazeer, Niki Parmar, Jakob Uszkoreit, Llion Jones, Aidan N. Gomez, Łukasz Kaiser, and Illia Polosukhin. 2017. Attention is all you need. InAdvances in Neural Information Processing Systems 30

    2017

  26. [34]

    Meng-Chen Wu and Yao-Wen Chang. 2004. Placement with align- ment and performance constraints using the B*-tree representation. In Proceedings of the 2004 International Conference on Computer Design

    2004

  27. [35]

    Ke Xue, Ruo-Tong Chen, Xi Lin, Yunqi Shi, Shixiong Kai, Siyuan Xu, and Chao Qian. 2024. Reinforcement learning policy as macro regulator rather than macro placer. InAdvances in Neural Information Processing Systems 37

    2024

  28. [36]

    Jackey Z Yan, Natarajan Viswanathan, and Chris Chu. 2009. Han- dling complexities in modern large-scale mixed-size placement. In Proceedings of the 46th Design Automation Conference

    2009

Pith tools

Reviewed July 1, 2026 · model on record in the stance chip above.