Recognition: unknown
Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL
Pith reviewed 2026-05-07 12:41 UTC · model grok-4.3
The pith
BZL integrates UVM, FPGA emulation and CI/CD into a continuous V&V loop for RISC-V pre-silicon validation.
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
Core claim
The paper describes an integrated V&V approach that places UVM-based RTL verification, FPGA-based system-level hardware-software validation, and CI/CD automation into a single industrial-grade loop. Running on extensive CPU and FPGA infrastructures, this loop supports ongoing refinement of RISC-V designs to achieve pre-silicon functional correctness and reliable co-integration of hardware and software.
What carries the argument
The V&V-in-the-Loop mechanism that combines UVM verification environment, FPGA validation platform, and CI/CD flow to automate and iterate on pre-silicon tests for RISC-V chips.
If this is right
- Thorough validation of RTL functionality through UVM.
- System-level pre-silicon hardware-software validation via FPGA.
- Continuous automation of builds, deployments, and tests via CI/CD.
- Scalable foundation for functional correctness in RISC-V designs.
- Support for European strategic initiatives in HPC chip design.
Where Pith is reading between the lines
- This approach may shorten development cycles by automating feedback across verification stages.
- Potential for application to other open instruction set architectures beyond RISC-V.
- Requires addressing practical integration hurdles between the three platforms for full effectiveness.
- Could serve as a template for collaborative open hardware verification projects.
Load-bearing premise
That linking UVM, FPGA, and CI/CD platforms into one loop will by itself produce reliable ongoing hardware and software integration without extra techniques or facing integration problems.
What would settle it
Finding that bugs in RISC-V designs still reach later stages despite the full loop running, or that the combined system cannot handle the scale of real production chip projects.
Figures
read the original abstract
The Barcelona Zetascale Lab (BZL) project aims to strengthening Europe's capacity in the design and manufacture of RISC-V based high-performance computing chips. In this context, we present a holistic pre-silicon verification and validation (V&V) methodology targeting highly robust RISC-V chip designs. This paper provides an overview of BZL's V&V approach, which integrates three complementary platforms: (1) a UVM-based verification environment to thoroughly validate RTL functionality; (2) an FPGA-based validation platform that enables system-level pre-silicon hardware-software RTL validation; and (3) a CI/CD flow that continuously automates build, deployment, and tests across these domains. By embedding these platforms into an industrial-grade V&V loop and exploiting large-scale CPU and FPGA hardware infrastructures, the BZL project enables continuous evolution of reliable hardware development and software integration. We believe that the BZL's V&V flow represents a robust and scalable foundation for ensuring the pre-silicon functional correctness and system level validation of RISC-V chip designs, and can serve as a key enabler for strategic initiatives in Europe, such as EPI and DARE, and beyond.
Editorial analysis
A structured set of objections, weighed in public.
Referee Report
Summary. The manuscript presents an overview of the Barcelona Zetascale Lab (BZL) project's holistic pre-silicon V&V methodology for RISC-V chip designs. It describes the integration of three platforms—a UVM-based environment for RTL functional validation, an FPGA-based platform for system-level hardware-software validation, and a CI/CD flow for automated build, deployment, and testing—into an industrial-grade continuous loop leveraging large-scale CPU and FPGA infrastructures. The central claim is that this V&V-in-the-Loop approach provides a robust and scalable foundation for ensuring functional correctness and can serve as a key enabler for European initiatives such as EPI and DARE.
Significance. If the described integration of UVM, FPGA, and CI/CD platforms can be shown to deliver reliable continuous verification, the work could provide a practical framework for pre-silicon validation of RISC-V designs, supporting strategic European HPC efforts. The clear high-level vision for combining complementary verification domains is a strength. However, the absence of any empirical results, metrics, or case studies means the significance remains prospective rather than demonstrated.
major comments (1)
- [Abstract] Abstract: The central assertion that the BZL V&V flow 'represents a robust and scalable foundation' for pre-silicon functional correctness is presented without any supporting data, results, error analysis, validation outcomes, or case studies, which is load-bearing for the paper's primary claim.
Simulated Author's Rebuttal
We thank the referee for their constructive review and for recognizing the high-level vision of integrating UVM, FPGA, and CI/CD platforms in the BZL project. We address the major comment on the abstract below.
read point-by-point responses
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Referee: [Abstract] Abstract: The central assertion that the BZL V&V flow 'represents a robust and scalable foundation' for pre-silicon functional correctness is presented without any supporting data, results, error analysis, validation outcomes, or case studies, which is load-bearing for the paper's primary claim.
Authors: We agree that the abstract's assertion is presented without quantitative supporting data, as this manuscript provides an overview of the BZL V&V-in-the-Loop architecture and its integration of the three platforms rather than specific empirical results or case studies. The claim is based on the complementary design of the UVM environment for RTL validation, the FPGA platform for hardware-software co-validation, and the CI/CD automation for continuous operation on large-scale infrastructures. To address this point, we will revise the abstract to present the contribution more precisely as a methodological framework whose robustness derives from the described integration, while moderating the language to indicate that it 'is designed to provide' or 'aims to establish' such a foundation. We will also note that detailed validation metrics and outcomes are intended for follow-on publications. This change will better reflect the paper's scope as a vision and architecture description. revision: yes
Circularity Check
No derivations, equations, or self-referential steps present
full rationale
The manuscript is a high-level project overview describing an intended integration of UVM, FPGA, and CI/CD platforms for RISC-V V&V. The sole central claim is an explicit belief statement ('We believe that the BZL's V&V flow represents a robust and scalable foundation...') rather than any derivation, prediction, or result obtained from prior steps. No equations, algorithms, fitted parameters, or load-bearing self-citations appear anywhere in the text. The description is self-contained as a forward-looking vision statement with no internal reduction to its own inputs.
Axiom & Free-Parameter Ledger
Reference graph
Works this paper leans on
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discussion (0)
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