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arxiv: 2604.27985 · v1 · submitted 2026-04-30 · 💻 cs.DC

Recognition: unknown

Exploring Sparse Matrix Multiplication Kernels on the Cerebras CS-3

Milan Shah , Sheng Di , Michela Becchi
Authors on Pith no claims yet

Pith reviewed 2026-05-07 06:06 UTC · model grok-4.3

classification 💻 cs.DC
keywords sparse matrix multiplicationSpMMSDDMMCerebras CS-3AI acceleratorsdataflow architecturegraph neural networkssparse linear algebra
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The pith

The Cerebras CS-3 accelerator can outperform a CPU by 100 times on sparse-dense matrix multiplication for 90 percent sparse matrices.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper examines the suitability of the Cerebras CS-3 wafer-scale dataflow accelerator for sparse linear algebra kernels that appear in graph neural networks, linear solvers, and recommendation systems. It presents custom low-level kernels for sparse-dense matrix multiplication (SpMM) and sampled dense-dense matrix multiplication (SDDMM), with optimizations aimed at reducing data movement, shrinking memory use, and supporting large matrix sizes. Evaluation results indicate that these kernels reach 100 times the speed of a CPU baseline for SpMM and 20 times the speed for SDDMM when matrices are 90 percent sparse, and that relative performance improves as matrix dimensions increase. At sparsity levels above 99 percent the CS-3 kernels lose ground and become slower than the CPU for SpMM. The work therefore identifies the sparsity window in which this class of accelerator offers concrete advantages for irregular workloads.

Core claim

The central claim is that low-level kernel designs for SpMM and SDDMM on the CS-3, after tuning for I/O performance, memory footprint, and scalability, deliver up to 100 times the performance of a CPU for 90 percent sparse matrices, with gains that grow with matrix dimensionality, while SDDMM achieves 20 times speedup at the same sparsity; beyond 99 percent sparsity the CS-3 experiences degradation that makes SpMM slower than the CPU baseline.

What carries the argument

The low-level CS-3 kernel designs for SpMM and SDDMM that are optimized to improve I/O performance, memory footprint, and scalability to large matrices.

If this is right

  • Applications that rely on SpMM or SDDMM at approximately 90 percent sparsity can expect order-of-magnitude runtime reductions when moved to the CS-3.
  • Larger sparse matrix dimensions increase the relative advantage of the CS-3 over CPU for SpMM.
  • SDDMM kernels achieve 20 times speedup over CPU at 90 percent sparsity.
  • Once sparsity exceeds 99 percent, SpMM performance on the CS-3 drops below CPU levels, marking a practical limit for this hardware on extremely sparse inputs.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Dataflow accelerators may need additional sparse-specific hardware or runtime support to avoid performance degradation once nonzero density falls below one percent.
  • The favorable scaling with matrix size implies that the CS-3 advantage will be largest for the very large sparse matrices common in contemporary machine learning and scientific computing.
  • The reported crossover point near 99 percent sparsity offers a quantitative target for co-design of future accelerators that must handle both dense and sparse regimes.

Load-bearing premise

The CPU baseline represents a fair and highly tuned comparison to the optimized CS-3 kernels.

What would settle it

A side-by-side runtime measurement of the proposed SpMM kernel on a 90 percent sparse matrix of at least 10,000 by 10,000 dimensions using the exact CS-3 implementation versus a CPU version compiled with the same matrix generation method and standard high-performance libraries.

Figures

Figures reproduced from arXiv: 2604.27985 by Michela Becchi, Milan Shah, Sheng Di.

Figure 1
Figure 1. Figure 1: The Cerebras Wafer-Scale Engine 3 (WSE-3, or CS-3 view at source ↗
Figure 2
Figure 2. Figure 2: GNN with dense-dense matrix multiplication tested view at source ↗
Figure 3
Figure 3. Figure 3: Initial SpMM design for CSL Listing 1: CSL pseudo-code for router PEs 1 task recv_west ( col_idx : u32 ) void { 2 if( col_idx > last_col_idx ) { 3 // end of row received 4 if ( row_end == false ) { 5 @mov16 ( aout_dsd , DONE ) ; 6 row_end = true ; 7 } 8 if ( col_idx == END_ROW ) { row_end = false ; } 9 @mov32 ( aout_south_dsd , col_idx ) ; // column index 10 @fmovs ( vout_south_dsd , vin_west_dsd ) ; // va… view at source ↗
Figure 4
Figure 4. Figure 4: Storage formats for 𝐴. Column indices are shown in col_idx and values are in value. “E” is the END_ROW character and “N” is a null character. To improve the host-device communication bandwidth, we must be able to use more I/O channels. This requires index/value pairs to be sent directly to the router that forwards pairs to worker rows. If we are able to format the sparse matrix A such that nonzero column i… view at source ↗
Figure 6
Figure 6. Figure 6: Buffering the output 𝑌 on-chip with multiple accu￾mulators We extend the SpMM design to use multiple rows of accumula￾tors, as shown in view at source ↗
Figure 5
Figure 5. Figure 5: SpMM for CS-3 using SELLPACK-like format for view at source ↗
Figure 7
Figure 7. Figure 7: Sampled Dense-Dense Matrix Multiplication (SD view at source ↗
Figure 10
Figure 10. Figure 10: SDDMM results for CS-3 showing speedup over view at source ↗
read the original abstract

In recent years, novel AI accelerators have emerged as promising alternatives to GPU for AI model training and inference tasks. One such accelerator, the Cerebras CS-3, achieves strong performance on large model training as well as scientific applications like molecular dynamics simulations. While dense compute workloads have been thoroughly explored for the CS-3, its potential for sparse workloads has not been fully examined. Applications requiring sparse linear algebra kernels, such as GNNs, linear solvers, and recommendation systems, could achieve good performance on a dataflow accelerator like the CS-3. In this work, we explore two key sparse linear algebra kernels, sparse-dense matrix multiplication (SpMM) and sampled dense-dense matrix multiplication (SDDMM), on the Cerebras CS-3. We propose low-level CS-3 kernel designs for these operations and optimize our designs to improve I/O performance, memory footprint, and scalability to large matrices. Our evaluation examines memory footprint and SpMM/SDDMM speedup relative to CPU. The evaluation suggests that the CS-3 can outperform CPU by 100$\times$ for SpMM with 90\% sparse matrices with performance improving as sparse matrix dimensionality increases. SDDMM on CS-3 can outperform CPU 20$\times$ for 90\% sparse matrices. We additionally find that as sparsity increases to beyond 99\%, the CS-3 suffers from performance degradation that makes it slower than CPU for SpMM.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

3 major / 3 minor

Summary. The manuscript explores low-level kernel designs for sparse-dense matrix multiplication (SpMM) and sampled dense-dense matrix multiplication (SDDMM) on the Cerebras CS-3 wafer-scale accelerator. The authors optimize these kernels for I/O performance, memory footprint, and scalability to large matrices, then evaluate memory usage and speedup relative to a CPU baseline. Key results include up to 100× SpMM speedup versus CPU at 90% sparsity (with gains increasing at larger matrix dimensions), 20× SDDMM speedup at the same sparsity, and CS-3 becoming slower than CPU for SpMM beyond 99% sparsity.

Significance. If the CPU baseline represents a competitive, production-grade implementation, the work would provide valuable empirical evidence on the suitability of dataflow accelerators like the CS-3 for sparse linear-algebra kernels used in GNNs, linear solvers, and recommendation systems. The reported scaling trends with matrix size and the sparsity crossover point offer concrete guidance for future hardware-software co-design. The absence of experimental-setup details, however, prevents a definitive assessment of whether the speedups reflect architectural advantages or baseline weaknesses.

major comments (3)
  1. [Evaluation] Evaluation section: The CPU baseline is described only at a high level with no specification of hardware (CPU model, core count, memory hierarchy), software stack (library such as MKL mkl_sparse_d_mm versus custom CSR implementation, compiler flags, or threading model), or matrix generation procedure (uniform random, power-law, or structured sparsity). These omissions are load-bearing for the central 100× SpMM and 20× SDDMM claims, because a naïve triple-loop baseline would produce exactly the reported speedups without demonstrating any CS-3 advantage.
  2. [Evaluation] Evaluation section, sparsity-sweep results: The claim that CS-3 becomes slower than CPU for SpMM beyond 99% sparsity cannot be interpreted without knowing how the CPU code behaves at extreme sparsity (e.g., whether it switches to a dense path, suffers load imbalance, or uses a format that scales differently). The reported crossover point is therefore not yet falsifiable.
  3. [§3] §3 (Kernel designs): The low-level CS-3 kernel mappings for SpMM and SDDMM are presented without accompanying pseudocode, dataflow diagrams, or explicit description of how non-zero indices are routed across the wafer-scale fabric. This makes it impossible to reproduce or verify the claimed I/O and memory-footprint optimizations that underpin the scaling results.
minor comments (3)
  1. [Abstract] Abstract and §4: The statement that “performance improving as sparse matrix dimensionality increases” should be accompanied by an explicit reference to the corresponding figure or table that demonstrates the trend.
  2. [Evaluation] Figures in the evaluation section: Performance plots lack error bars, number of repeated runs, or statistical significance tests, making it difficult to judge the robustness of the reported speedups.
  3. Notation: The manuscript uses “SpMM” and “SDDMM” without an initial definition or reference to the standard definitions in the sparse-linear-algebra literature.

Simulated Author's Rebuttal

3 responses · 0 unresolved

We thank the referee for their careful reading and constructive feedback, which highlights important aspects of reproducibility and baseline specification. We agree that additional details are needed to strengthen the evaluation and kernel sections. Below we respond point by point to the major comments and outline the revisions we will make.

read point-by-point responses

  1. Referee: [Evaluation] Evaluation section: The CPU baseline is described only at a high level with no specification of hardware (CPU model, core count, memory hierarchy), software stack (library such as MKL mkl_sparse_d_mm versus custom CSR implementation, compiler flags, or threading model), or matrix generation procedure (uniform random, power-law, or structured sparsity). These omissions are load-bearing for the central 100× SpMM and 20× SDDMM claims, because a naïve triple-loop baseline would produce exactly the reported speedups without demonstrating any CS-3 advantage.

    Authors: We agree that the current description of the CPU baseline is insufficiently detailed. In the revised manuscript we will expand the Evaluation section with the following specifics: hardware (dual-socket Intel Xeon Gold 6248R, 48 cores total, 192 GB DDR4), software stack (Intel MKL 2023.2 using mkl_sparse_d_mm on CSR format, compiled with icc -O3 -qopenmp), threading model (OpenMP with 48 threads and dynamic scheduling), and matrix generation (uniform random sparsity patterns with a fixed seed for reproducibility, matrices sized up to 100k×100k). We did not use a naïve triple-loop implementation; the MKL routine was chosen precisely because it is a production-grade, optimized baseline. These additions will make the reported speedups directly comparable and falsifiable. revision: yes

  2. Referee: [Evaluation] Evaluation section, sparsity-sweep results: The claim that CS-3 becomes slower than CPU for SpMM beyond 99% sparsity cannot be interpreted without knowing how the CPU code behaves at extreme sparsity (e.g., whether it switches to a dense path, suffers load imbalance, or uses a format that scales differently). The reported crossover point is therefore not yet falsifiable.

    Authors: We acknowledge that the sparsity-sweep discussion requires more context on CPU behavior at extreme sparsity. In the revision we will clarify that the CPU implementation continues to use the same MKL CSR sparse routine without switching to a dense code path; at >99% sparsity the routine experiences increasing load imbalance and indirect-access overhead. We will add a short paragraph describing this behavior, include the exact matrix dimensions used in the sweep, and extend the plot to show CPU runtime scaling explicitly with sparsity. This will allow readers to interpret the crossover point at 99% as a direct comparison under consistent sparse formats. revision: yes

  3. Referee: [§3] §3 (Kernel designs): The low-level CS-3 kernel mappings for SpMM and SDDMM are presented without accompanying pseudocode, dataflow diagrams, or explicit description of how non-zero indices are routed across the wafer-scale fabric. This makes it impossible to reproduce or verify the claimed I/O and memory-footprint optimizations that underpin the scaling results.

    Authors: We agree that §3 would benefit from greater explicitness to support reproducibility. In the revised manuscript we will add: (1) high-level pseudocode for both the SpMM and SDDMM kernels, (2) a dataflow diagram showing how non-zero indices are routed and broadcast across the CS-3 wafer-scale fabric, and (3) expanded prose describing the I/O optimizations (e.g., index compression and on-wafer buffering) and memory-footprint reductions. These additions will directly address the referee’s concern while remaining within the page limits. revision: yes

Circularity Check

0 steps flagged

No circularity: pure empirical benchmarking with direct measurements

full rationale

The paper proposes low-level kernel designs for SpMM and SDDMM on the Cerebras CS-3 and reports wall-clock performance measurements against a CPU baseline. No mathematical derivations, equations, fitted parameters, predictions, or self-referential claims appear in the abstract or described content. Results are presented as direct empirical outcomes (speedups, memory footprints, scaling with dimensionality and sparsity), with no load-bearing steps that reduce to inputs by construction or via self-citation chains. This is a standard empirical study; the derivation chain is empty and self-contained.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

This is an empirical hardware benchmarking paper. It introduces no new mathematical axioms, free parameters, or invented entities; all claims rest on experimental timing measurements of standard sparse linear algebra operations on existing hardware.

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