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arxiv: 2605.04213 · v1 · submitted 2026-05-05 · 💻 cs.AR

Recognition: 3 theorem links

· Lean Theorem

The Anatomy of Silent Data Corruption: GPU Error Pattern Study and Modeling Guidance

Chung-Hsuan Tung , Yanxiang Huang , Nirmal Saxena , Philip Shirvani , Saurabh Hukerikar , Twinkle Jain , Abhishek Tyagi , Sanjay Gongalore
Authors on Pith no claims yet

Pith reviewed 2026-05-08 17:59 UTC · model grok-4.3

classification 💻 cs.AR
keywords silent data corruptionGPU reliabilityfault injectionbit-flip patternsdata center GPUserror modelingresilience evaluation
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The pith

Large-scale GPU fault injection shows silent corruptions rarely produce NaN or infinity values and exhibit multi-bit flips with periodic addresses.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper runs millions of hours of stuck-at fault injection on a data-center GPU across 63 micro-benchmarks to map the actual patterns of silent data corruption. It reports that NaN, positive infinity, and negative infinity appear in only 1.01 percent of cases, single-bit flips occur in fewer than 40 percent of events, and corrupted memory addresses repeat at regular intervals. These measurements matter because current high-level error models often assume simpler behaviors that do not match the observed distributions. If the patterns hold, then resilience testing for large GPU clusters must shift toward injection methods that reproduce the full range of outcomes rather than relying on narrow assumptions about floating-point specials or isolated bit flips.

Core claim

A campaign of over three million simulator hours of gate-level stuck-at fault injection on production-class data-center GPUs and 63 CUDA micro-benchmarks establishes that NaN/+INF/-INF outcomes constitute only 1.01% of silent data corruptions, single-bit flips account for less than 40% of all bit-flip events, and corruption addresses display clear periodicity. These statistics are extracted from corruption types, bit-flip behavior, and warp-aligned spatial correlations, directly motivating the construction of distribution-aware high-level fault models and realistic software-based fault injection techniques for evaluating GPU resilience.

What carries the argument

Gate-level stuck-at fault injection performed across 63 CUDA micro-benchmarks on a production-class data-center GPU, used to collect statistics on corruption outcome types, bit-flip multiplicity, and periodic address patterns.

If this is right

  • High-level fault models must incorporate the full observed distribution of corruption outcomes instead of focusing primarily on NaN and infinity values.
  • Software-based fault injection campaigns should replicate multi-bit flips and periodic address patterns to produce realistic resilience estimates.
  • Resilience evaluations for production GPU architectures can use these empirical distributions to guide targeted error detection and recovery mechanisms.
  • Micro-benchmark results provide a basis for scaling fault models to larger workloads while preserving the measured bit-flip and spatial characteristics.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If the periodic address pattern arises from fixed hardware structures, targeted hardware monitoring at those locations could detect corruptions earlier than generic checks.
  • The low rate of special-value corruptions suggests that floating-point exception handlers alone will miss most silent errors in large-scale training runs.
  • Extending the injection methodology to full application workloads instead of micro-benchmarks would test whether the same distributions appear outside controlled settings.

Load-bearing premise

Gate-level stuck-at fault injection on micro-benchmarks accurately captures the distribution and spatial patterns of real silent data corruptions that occur in production data-center GPUs running full workloads.

What would settle it

Direct measurement of silent data corruptions during real production GPU workloads that shows NaN or infinity values occurring at rates well above 1.01% or lacking periodic address structure would contradict the reported statistics.

Figures

Figures reproduced from arXiv: 2605.04213 by Abhishek Tyagi, Chung-Hsuan Tung, Nirmal Saxena, Philip Shirvani, Sanjay Gongalore, Saurabh Hukerikar, Twinkle Jain, Yanxiang Huang.

Figure 1
Figure 1. Figure 1: Fault injection and error pattern extraction flow. We an view at source ↗
Figure 2
Figure 2. Figure 2: Corruption types across 63 micro-benchmarks. NaN, view at source ↗
Figure 3
Figure 3. Figure 3: The corruption type when faults are in specific hard view at source ↗
Figure 5
Figure 5. Figure 5: The probability of bit-flips of each bit position. Top to view at source ↗
Figure 4
Figure 4. Figure 4: The corruption type when faults are in specific hard view at source ↗
Figure 6
Figure 6. Figure 6: The probability of bit-flip counts per corrupted value. view at source ↗
Figure 7
Figure 7. Figure 7: The corruption rate (y-axis of each sub-figure) of each memory address when modulo the warp size view at source ↗
Figure 8
Figure 8. Figure 8: Software FI guided by gate-level error statistics. view at source ↗
read the original abstract

Silent data corruption (SDC) threatens the reliability of large-scale GPU clusters used for training large language models, yet its rarity and lack of explicit error signals make accurate high-level modeling challenging. To address this gap, we conducted a large-scale gate-level stuck-at fault injection on a production-class data-center GPU, consuming over three million simulator hours across 63 CUDA micro-benchmarks. We extracted GPU SDC characteristics in terms of corruption types, bit-flip behavior, and warp-aligned spatial correlation. Our results show that NaN/+INF/-INF account for only 1.01% of SDC outcomes, that single-bit flips constitute less than 40% of bit-flip events, and that corruption addresses exhibit periodicity. These statistics motivate distribution-aware high-level fault modeling and realistic software-based fault injection for resilience evaluation of production-class GPU architectures.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 1 minor

Summary. The manuscript reports results from a large-scale gate-level stuck-at fault injection campaign consuming over three million simulator hours across 63 CUDA micro-benchmarks on a production-class data-center GPU. It claims that NaN/+INF/-INF account for only 1.01% of SDC outcomes, single-bit flips constitute less than 40% of bit-flip events, and corruption addresses exhibit periodicity. These empirical statistics are presented as motivation for distribution-aware high-level fault modeling and realistic software-based fault injection for resilience evaluation of production GPUs.

Significance. If the observed patterns are representative, the study offers concrete, large-scale empirical data on SDC characteristics that could improve high-level fault models beyond simplistic assumptions. The scale of the simulation campaign (over 3M simulator hours) is a clear strength, providing direct counts rather than purely theoretical derivations, which could help guide more accurate resilience techniques for data-center GPU workloads.

major comments (1)
  1. [Abstract and Methods] Abstract and Methods: The headline statistics and call for distribution-aware modeling rest on the representativeness of gate-level stuck-at injection in 63 micro-benchmarks. However, the manuscript does not validate these distributions against real field SDC logs from production GPUs or compare them to alternative mechanisms such as transient soft errors or voltage droops under full-scale workloads (e.g., LLM training kernels). Micro-benchmarks exercise narrower control flow and utilization than production code, making generalization a load-bearing assumption for the modeling guidance.
minor comments (1)
  1. [Abstract] The abstract would benefit from stating the total number of fault injections performed to better contextualize the reported percentages such as 1.01%.

Simulated Author's Rebuttal

1 responses · 1 unresolved

We thank the referee for the constructive feedback and for recognizing the scale of our simulation campaign. We address the major comment below.

read point-by-point responses

  1. Referee: [Abstract and Methods] Abstract and Methods: The headline statistics and call for distribution-aware modeling rest on the representativeness of gate-level stuck-at injection in 63 micro-benchmarks. However, the manuscript does not validate these distributions against real field SDC logs from production GPUs or compare them to alternative mechanisms such as transient soft errors or voltage droops under full-scale workloads (e.g., LLM training kernels). Micro-benchmarks exercise narrower control flow and utilization than production code, making generalization a load-bearing assumption for the modeling guidance.

    Authors: We agree that the choice of micro-benchmarks and the stuck-at fault model limits direct generalization to all production scenarios. The 63 micro-benchmarks were selected to enable exhaustive, controlled injection across diverse CUDA primitives and utilization levels while remaining computationally feasible; full-scale kernels such as LLM training would make the 3M+ simulator-hour campaign intractable. The reported statistics are presented as empirical observations from this specific injection methodology to motivate distribution-aware modeling, not as universal claims. We will revise the manuscript to add an explicit limitations subsection discussing the scope (stuck-at faults, micro-benchmarks), the absence of direct comparison to transient soft errors or voltage droops, and the value of future validation against real field data. revision: partial

standing simulated objections not resolved
  • Validation of the observed distributions against real field SDC logs from production GPUs, as such detailed proprietary data is not available to the authors.

Circularity Check

0 steps flagged

No circularity: empirical counts from fault-injection campaign

full rationale

The paper reports direct observational statistics obtained from over three million simulator hours of gate-level stuck-at fault injection across 63 CUDA micro-benchmarks. Key results (NaN/+INF/-INF fraction of 1.01%, single-bit flips <40% of events, address periodicity) are presented as raw counts and spatial patterns extracted from the injection outcomes. No equations, parameter fits, or derivations are claimed; the text contains no self-citation load-bearing steps, uniqueness theorems, or ansatzes that reduce any result to its own inputs by construction. The study is therefore self-contained as a measurement campaign.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The study rests on the standard assumption that stuck-at faults at gate level are a reasonable proxy for real SDC; no free parameters or new entities are introduced.

axioms (1)
  • domain assumption Gate-level stuck-at fault injection produces error patterns representative of real silent data corruption in production GPUs
    Invoked when the authors extrapolate from micro-benchmark results to high-level modeling guidance.

pith-pipeline@v0.9.0 · 5470 in / 1314 out tokens · 76480 ms · 2026-05-08T17:59:32.789666+00:00 · methodology

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Lean theorems connected to this paper

Citations machine-checked in the Pith Canon. Every link opens the source theorem in the public Lean library.

  • Foundation/Breath1024.lean (period8 := 8) period8 unclear
    ?
    unclear

    Relation between the paper passage and the cited Recognition theorem.

    Grouping corrupted addresses modulo the warp size (W=32) reveals periodic corruption patterns at the warp granularity... periodicity at multiple granularities, e.g., 16, 8, 4, 2

What do these tags mean?
matches
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supports
The theorem supports part of the paper's argument, but the paper may add assumptions or extra steps.
extends
The paper goes beyond the formal theorem; the theorem is a base layer rather than the whole result.
uses
The paper appears to rely on the theorem as machinery.
contradicts
The paper's claim conflicts with a theorem or certificate in the canon.
unclear
Pith found a possible connection, but the passage is too broad, indirect, or ambiguous to say the theorem truly supports the claim.

Reference graph

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