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arxiv: 2605.05119 · v1 · submitted 2026-05-06 · 💻 cs.AR

Recognition: unknown

MCFlash: Bulk Bitwise Processing in 3D NAND with Dynamic Sensing and Multi-level Encoding

Habib Ur Rahman , Tharini Suresh , Sudeep Pasricha , Biswajit Ray
Authors on Pith no claims yet

Pith reviewed 2026-05-08 16:00 UTC · model grok-4.3

classification 💻 cs.AR
keywords 3D NAND flashbitwise operationsin-memory computingmulti-level celldynamic sensingbulk processingcommercial NANDon-chip logic
0
0 comments X

The pith

MCFlash performs bulk bitwise operations directly inside commercial 3D NAND flash chips using only standard user-mode instructions.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper shows that off-the-shelf 3D NAND memory can run large-scale bitwise logic such as AND, OR, and XOR without moving data out to a separate processor. It achieves this by storing data in multiple charge levels per cell and adjusting the voltages used to sense those levels on the fly. A sympathetic reader would care because most data movement between memory and compute units wastes time and energy; keeping simple logic inside the storage array could shrink that cost for workloads that scan or combine huge bit vectors. The authors test the method on multiple real chips and report it stays reliable for over a billion operations on new blocks and for thousands of program-erase cycles afterward.

Core claim

MCFlash is a technique that executes bulk bitwise operations directly within commercial off-the-shelf 3D NAND flash chips. It relies solely on standard user-mode instructions, combining Multi-Level Cell data encodings with dynamically tuned read reference voltages to execute in-place bitwise operations. Evaluations across diverse NAND chips, both floating-gate and charge-trap, demonstrate error-free operation sustaining over one billion operations on fresh blocks and bit-error rates below 0.015 percent even after 10,000 program/erase cycles.

What carries the argument

The pairing of multi-level cell charge encodings with on-the-fly adjustment of read reference voltages that turns standard sense operations into bitwise logic gates performed inside the NAND array itself.

If this is right

  • Bulk bitwise operations become possible without moving data between the NAND array and an external processor.
  • Energy and latency costs for scans and reductions over large bit vectors drop because computation stays inside the memory.
  • The same approach works across floating-gate and charge-trap cell technologies from different generations.
  • Reliability holds for more than a billion operations on fresh blocks and continues after heavy wear.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Storage arrays could act as simple compute units for database filters or neural-network bit packing without extra hardware.
  • Chaining several bitwise steps inside the array might support wider arithmetic without leaving the chip.
  • Power savings in large-scale analytics systems would grow if the method scales to entire planes or dies running in parallel.

Load-bearing premise

That any commercial 3D NAND chip will accept and correctly respond to the same user-mode read commands and voltage settings without hidden internal behaviors that would break the bitwise results.

What would settle it

Running the described bitwise sequences on a new commercial 3D NAND chip model, applying the same dynamic voltage adjustments through ordinary commands, and checking whether the output bit-error rate stays below 0.015 percent after 10,000 program-erase cycles; failure on either fresh or aged blocks would disprove the central claim.

read the original abstract

This paper presents MCFlash, a practical and immediately deployable technique for executing bulk bitwise operations directly within commercial off-the-shelf(COTS) 3D NAND flash chips. MCFlash relies solely on standard user-mode instructions, combining Multi-Level Cell (MLC) data encodings with dynamically tuned read reference voltages to execute in-place bitwise operations. We evaluate MCFlash across diverse NAND flash chips, both floating-gate and charge-trap variants, from different generations. Our results represent the first demonstration of error-free, on-chip bitwise operations, sustaining over one billion operations on fresh blocks and maintaining bit-error rates below 0.015% even after 10,000 program/erase (P/E) cycles.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The manuscript presents MCFlash, a technique for performing bulk bitwise operations directly inside commercial off-the-shelf 3D NAND flash chips. It combines multi-level cell encodings with dynamically tuned read reference voltages applied via standard user-mode instructions, and reports error-free execution of over one billion operations on fresh blocks together with bit-error rates below 0.015% after 10,000 P/E cycles across both floating-gate and charge-trap devices from multiple generations.

Significance. If the central claims are substantiated, the work would constitute a meaningful advance in in-memory computing for NAND-based systems by demonstrating a practical, hardware-agnostic method for on-chip bitwise processing that requires no custom silicon and exhibits strong endurance. The cross-generation, cross-technology evaluation is a positive feature that supports broader applicability.

major comments (2)
  1. [Methods] Methods section (voltage tuning procedure): the claim that bitwise operations are performed using only standard user-mode instructions plus dynamically tuned read voltages is load-bearing for both the 'immediately deployable on COTS' assertion and the 'first demonstration' status, yet the manuscript provides insufficient detail on the exact command sequences, calibration steps, and safeguards against FTL intervention or vendor-specific restrictions. Without this, it is impossible to confirm that the tuning does not rely on non-standard access unavailable in normal operation.
  2. [Evaluation] Evaluation / Results section: the abstract states concrete metrics (error-free operation for >1 billion cycles, BER < 0.015% after 10k P/E), but the manuscript lacks accompanying data tables, statistical summaries, or raw measurement logs that would allow independent verification of these numbers under the stated conditions.
minor comments (1)
  1. [Abstract] The abstract would benefit from explicitly naming the bitwise operations (AND, OR, XOR, etc.) demonstrated so that the scope of the claimed error-free execution is immediately clear.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback and for recognizing the potential significance of MCFlash as a practical in-memory computing approach on COTS 3D NAND. We address each major comment point by point below and outline the revisions we will make to improve clarity and verifiability.

read point-by-point responses

  1. Referee: [Methods] Methods section (voltage tuning procedure): the claim that bitwise operations are performed using only standard user-mode instructions plus dynamically tuned read voltages is load-bearing for both the 'immediately deployable on COTS' assertion and the 'first demonstration' status, yet the manuscript provides insufficient detail on the exact command sequences, calibration steps, and safeguards against FTL intervention or vendor-specific restrictions. Without this, it is impossible to confirm that the tuning does not rely on non-standard access unavailable in normal operation.

    Authors: We agree that the current Methods section would benefit from greater specificity to allow readers to reproduce the exact procedure. In the revised manuscript we will add a dedicated subsection that enumerates the precise sequence of standard user-mode NAND commands (including the read, program, and erase opcodes issued through the standard interface), the iterative calibration algorithm used to select the dynamic read reference voltages for each multi-level encoding, and the explicit steps taken to operate on raw blocks while disabling or bypassing file-system and FTL layers (e.g., by using direct block-level access on unmounted devices). These additions will be supported by pseudocode and timing diagrams so that the claim of standard-instruction-only operation can be independently verified. revision: yes

  2. Referee: [Evaluation] Evaluation / Results section: the abstract states concrete metrics (error-free operation for >1 billion cycles, BER < 0.015% after 10k P/E), but the manuscript lacks accompanying data tables, statistical summaries, or raw measurement logs that would allow independent verification of these numbers under the stated conditions.

    Authors: The aggregate results are derived from repeated trials across multiple devices and P/E points, but we concur that tabular presentation and statistical detail would strengthen verifiability. The revised manuscript will include new tables that report, for each device generation and technology, the mean BER, standard deviation, number of trials, and total operations performed at 0, 1k, 5k, and 10k P/E cycles. A supplementary data file containing per-trial BER logs for a representative subset of experiments will also be provided. Full raw traces exceed practical appendix size; therefore we will make a curated subset available upon request while ensuring the tables allow direct confirmation of the reported thresholds. revision: partial

Circularity Check

0 steps flagged

No circularity: experimental hardware technique with no equations or fitted predictions

full rationale

The paper describes an empirical hardware technique for in-place bitwise operations on COTS 3D NAND using standard user-mode commands and dynamic read-voltage tuning. No mathematical derivation chain, equations, parameters fitted to subsets of data, or self-citation load-bearing premises are present. Claims rest on direct measurements across multiple chip generations and types, with error rates reported from physical experiments rather than any constructed prediction that reduces to the inputs. This is the expected non-finding for a purely experimental systems paper.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

The contribution is an experimental hardware technique that exploits existing NAND cell behavior; no new mathematical axioms, free parameters, or invented physical entities are introduced.

pith-pipeline@v0.9.0 · 5426 in / 1076 out tokens · 47907 ms · 2026-05-08T16:00:14.328347+00:00 · methodology

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