arxiv: 2605.05374 · v1 · submitted 2026-05-06 · 💻 cs.AR

Recognition: unknown

An Open-Source Flow for Single-Phase, Edge-Triggered to Two-Phase, Non-Overlapping Clocking Conversion

Paolo Pedroso , Lee-Way Wang , Matthew Guthaus

Authors on Pith no claims yet

Pith reviewed 2026-05-08 15:47 UTC · model grok-4.3

classification 💻 cs.AR

keywords two-phase clockinglatch-based designsclock conversionRTL to GDS flowpower reductiontiming closurenon-overlapping clocks

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The pith

An automated flow converts flip-flop-based RTL designs into two-phase non-overlapping latch-based clocking while preserving functionality.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper seeks to establish a complete automated method for switching from single-phase edge-triggered clocking to two-phase clocking. Two-phase clocking provides advantages in timing margin and flexibility but is hard to adopt without automation. The method handles the conversion automatically along with physical design and validation. A sympathetic reader would care because it removes the barrier of manual complexity that has kept two-phase clocking uncommon in practice.

Core claim

The paper claims that an integrated flow can automatically transform flip-flop-based RTL into two-phase latch-based designs. It performs mapping and retiming to create latch equivalents, generates dual clock trees for non-overlapping phases, validates the two-phase correctness, and performs full physical design. Clock-gated and recirculation variants are implemented, with the clock-gated one showing power and area benefits, and the approach allowing timing closure via time borrowing on designs that fail with flip-flops.

What carries the argument

The automated conversion pipeline that maps edge-triggered elements to non-overlapping latches and synthesizes separated clock phases.

Load-bearing premise

The automated transformation steps preserve the original functionality and timing requirements exactly, without introducing bugs that the validation misses.

What would settle it

Simulating the output design and comparing its behavior to the original flip-flop version under various inputs to check for functional mismatches, or attempting to close timing on the failing design and verifying the result.

Figures

Figures reproduced from arXiv: 2605.05374 by Lee-Way Wang, Matthew Guthaus, Paolo Pedroso.

**Figure 1.** Figure 1: Time-borrowing example. 2.3 Retiming Since our framework involves a series of technology mapping and retiming steps that progressively transform and rename cells throughout the flow, we introduce the following naming conventions similar to Yosys [16] to track cell types across each stage: • DFF_baseΦ𝑛 : Base posedge D flip-flop(s) (i.e. _DFF_P_) prior to mapping to latches, where 𝑛 denotes the clock phase… view at source ↗

**Figure 2.** Figure 2: Minimum-delay retiming: (a) before and (b) after view at source ↗

**Figure 3.** Figure 3: Minimum-area retiming: (a) before and (b) after view at source ↗

**Figure 4.** Figure 4: Two-phase front-end flow. 3.1 Frontend: Synthesis and Clock Conversion The front-end uses Yosys techmap to duplicate and transform flipflops, and ABC retime to redistribute sequential elements after duplication [2, 17]. We present the full frontend methodology in view at source ↗

**Figure 5.** Figure 5: Recirculation mux duplication (a), recirculation mux transformation (b), clock-gated duplication/transformation (c). view at source ↗

**Figure 6.** Figure 6: Power trade-off of two-phase latch variants over flip-flops; clock-gating reduces total power compared to recirculation view at source ↗

read the original abstract

Two-phase clocking offers significant advantages in timing margin and clock flexibility, yet its adoption remains limited due to the absence of automation in modern design flows. Managing strict non-overlap and 180$^\circ$ phase separation introduces complexity in RTL implementation and timing closure, leaving two-phase clocking rare in practice. This paper presents the first fully automated two-phase clocking flow integrated into OpenROAD Flow Scripts (ORFS). Our methodology automatically transforms flip-flop-based RTL into two-phase latch-based designs using Yosys technology mapping, ABC retiming, dual clock tree synthesis, two-phase correctness validation, and full physical design from RTL-to-GDS. We implement clock-gated and recirculation mux variants, where clock-gated achieves an average 29.2\% power reduction and 50\% latch count reduction over recirculation mux. Both variants are compared against flip-flop baselines, demonstrating timing closure through time borrowing on a design that failed timing with flip-flops.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

This paper ships the first complete automated FF-to-two-phase-latch flow inside OpenROAD, with measured power and latch-count wins, but the functional-equivalence checks need more explicit description.

read the letter

The core thing here is a working end-to-end script set that takes ordinary flip-flop RTL, maps it through Yosys and ABC into two-phase latches, builds dual clock trees, runs a validation step, and produces GDS. They show two concrete variants and report that the clock-gated one cuts power by 29.2 % on average while using half as many latches as the recirculation-mux version. They also close timing on at least one design that failed with flip-flops, thanks to time borrowing. That is new for the open-source OpenROAD Flow Scripts stack; prior work was either manual or only partial.

Referee Report

2 major / 2 minor

Summary. The paper claims to present the first fully automated open-source flow, integrated into OpenROAD Flow Scripts (ORFS), that converts single-phase edge-triggered flip-flop RTL designs into two-phase non-overlapping latch-based designs. The flow uses Yosys technology mapping, ABC retiming, dual clock tree synthesis, a two-phase correctness validation step, and complete RTL-to-GDS physical design. It evaluates clock-gated and recirculation-mux variants, reporting an average 29.2% power reduction and 50% latch-count reduction for the clock-gated version, plus successful timing closure via time borrowing on a design that failed with conventional flip-flops.

Significance. If the functional-equivalence and timing claims hold, the work would be significant for the open-source EDA community: it removes a long-standing automation barrier to two-phase clocking, supplies a reproducible RTL-to-GDS pipeline inside ORFS, and demonstrates concrete power and timing benefits on at least one failing design. The open-source release itself is a clear strength that enables independent verification and extension.

major comments (2)

[Abstract / Results] Abstract and Results section: the concrete claims of 29.2% average power reduction and 50% latch-count reduction are presented without any list of benchmark designs, their sizes or characteristics, number of trials, or error bars. Because these numbers are the primary empirical support for the flow's value, the absence of this information makes the generality and statistical reliability of the results impossible to assess from the manuscript.
[Methodology] Methodology section (description of the two-phase correctness validation): the paper states that the Yosys/ABC transformation plus dual-CTS produces a functionally equivalent and timing-safe netlist, yet provides no concrete description of what the validation actually checks (formal equivalence checking against the original RTL, exhaustive or directed simulation, structural non-overlap rules only, etc.). This verification step is load-bearing for every reported power, area, and timing result; without its details the preservation assumption remains unverified.

minor comments (2)

[Introduction] The abstract and introduction should explicitly cite prior automated or semi-automated two-phase flows (even if limited) so that the novelty claim of being the 'first fully automated' flow can be evaluated against the literature.
[Results] Figure captions and tables lack units or normalization details for power and area numbers, making direct comparison with the flip-flop baseline difficult.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback. We agree that additional details on benchmarks and validation are needed to strengthen the manuscript and will revise accordingly.

read point-by-point responses

Referee: [Abstract / Results] Abstract and Results section: the concrete claims of 29.2% average power reduction and 50% latch-count reduction are presented without any list of benchmark designs, their sizes or characteristics, number of trials, or error bars. Because these numbers are the primary empirical support for the flow's value, the absence of this information makes the generality and statistical reliability of the results impossible to assess from the manuscript.

Authors: We agree that the absence of benchmark details limits assessment of generality and reliability. In the revised manuscript we will add a table in the Results section listing all designs (with gate counts, flip-flop/latch counts, and other characteristics), the number of trials per design, and error bars or standard deviations on the reported averages. This will make the 29.2% power reduction and 50% latch-count reduction claims fully transparent. revision: yes
Referee: [Methodology] Methodology section (description of the two-phase correctness validation): the paper states that the Yosys/ABC transformation plus dual-CTS produces a functionally equivalent and timing-safe netlist, yet provides no concrete description of what the validation actually checks (formal equivalence checking against the original RTL, exhaustive or directed simulation, structural non-overlap rules only, etc.). This verification step is load-bearing for every reported power, area, and timing result; without its details the preservation assumption remains unverified.

Authors: We acknowledge the validation description is insufficient. The process uses Yosys formal equivalence checking against the original RTL, structural non-overlap verification on the dual clock phases, and static timing analysis to confirm safe time borrowing. We will expand the Methodology section with a dedicated subsection detailing these exact checks, tools, and pass criteria so that functional equivalence and timing safety are explicitly verified for all results. revision: yes

Circularity Check

0 steps flagged

No circularity: engineering flow with empirical results

full rationale

The paper describes an automated RTL-to-GDS conversion flow using Yosys techmapping, ABC retiming, dual CTS, and validation steps, then reports measured power (29.2%), latch count (50%), and timing improvements versus flip-flop baselines. No equations, fitted parameters, or predictions appear; results are direct experimental outcomes from the implemented flow rather than derivations that reduce to the same inputs by construction. No self-citations, uniqueness theorems, or ansatzes are invoked as load-bearing premises. The central claims rest on tool integration and benchmark data, which are externally verifiable and independent of the reported numbers.

Axiom & Free-Parameter Ledger

0 free parameters · 2 axioms · 0 invented entities

The central claim rests on standard VLSI assumptions about RTL equivalence after mapping and retiming, plus tool correctness for clock tree synthesis and validation; no new physical constants or fitted parameters are introduced in the abstract.

axioms (2)

domain assumption The original flip-flop RTL functionality is preserved by the Yosys/ABC transformation to latch-based two-phase logic
Invoked when claiming the converted designs are equivalent.
domain assumption Two-phase correctness validation is sufficient to guarantee absence of functional or timing errors
Used to assert that the generated designs are valid.

pith-pipeline@v0.9.0 · 5471 in / 1376 out tokens · 43707 ms · 2026-05-08T15:47:49.452016+00:00 · methodology

discussion (0)

Reference graph

Works this paper leans on

18 extracted references · 4 canonical work pages

[1]

Hurst et al

A. Hurst et al. 2006. The Advantages of Latch-Based Design Under Process Variation. InDAC. ACM

2006
[2]

Hurst et al

A. Hurst et al. 2007. Fast Minimum-Register Retiming via Binary Maximum-Flow. InIWLS

2007
[3]

Wolf et al

C. Wolf et al. 2013. Yosys – A Free Verilog Synthesis Suite. InAustrochip. https: //github.com/YosysHQ/yosys

2013
[4]

Harris et al

D. Harris et al. 1999. Timing Analysis Including Clock Skew.TCAD18, 11 (1999), 1608–1618. doi:10.1109/43.806806

work page doi:10.1109/43.806806 1999
[5]

Singh et al

K. Singh et al. 2018. Low Power Latch Based Design with Smart Retiming. In ISQED. IEEE, 329–334. doi:10.1109/ISQED.2018.8357308

work page doi:10.1109/isqed.2018.8357308 2018
[6]

Brayton et al

R. Brayton et al. 2010. ABC: An Academic Industrial-Strength Verification Tool. InCA V (LNCS, Vol. 6174). Springer, 24–40. doi:10.1007/978-3-642-14295-6_5

work page doi:10.1007/978-3-642-14295-6_5 2010
[7]

Ajayi et al

T. Ajayi et al. 2019. OpenROAD: Toward a Self-Driving, Open-Source Digital Layout Implementation Tool Chain.GOMACTECH(2019), 1105–1110

2019
[8]

Friedman

E. Friedman. 2001. Clock Distribution Networks in Synchronous Digital Inte- grated Circuits.Proc. IEEE89, 5 (2001), 665–692. doi:10.1109/5.929649

work page doi:10.1109/5.929649 2001
[9]

Horowitz

M. Horowitz. 2025. Lecture 7: Clocking of VLSI Systems. Lecture notes, EE271, Stanford University. 271clockingnotes.pdf

2025
[10]

OpenROAD Project. 2025. OpenROAD API. https://openroad.readthedocs.io/en/ latest/main/README2.html. Accessed Sept. 2025

2025
[11]

SkyWater Technology. 2025. Libraries. https://skywater-pdk.readthedocs.io/en/ main/contents/libraries.html. Accessed Aug. 2025

2025
[12]

The OpenROAD Project. 2019. OpenDB: Database and Tool Framework for EDA. https://github.com/The-OpenROAD-Project/OpenDB/tree/master. Accessed: 2026-03-02

2019
[13]

The OpenROAD Project. 2025. TritonCTS: Clock Tree Synthesis. https://github. com/The-OpenROAD-Project/TritonCTS. Accessed Aug. 2025

2025
[14]

2026.OpenROAD: RTL-to-GDS Flow

The OpenROAD Project. 2026.OpenROAD: RTL-to-GDS Flow. Retrieved February 17, 2026 from https://github.com/The-OpenROAD-Project/OpenROAD

2026
[15]

W. Wolf. 2009.Modern VLSI Design: IP-Based Design(4 ed.). Pearson, Westford, MA

2009
[16]

YosysHQ. 2024. simcells.v. GitHub. https://github.com/YosysHQ/yosys/blob/ main/techlibs/common/simcells.v

2024
[17]

2024.techmap — Yosys 0.35 Documentation

YosysHQ. 2024.techmap — Yosys 0.35 Documentation. https://yosyshq. readthedocs.io/projects/yosys/en/0.35/cmd/techmap.html

2024
[18]

YosysHQ. 2025. Equivalence Checking. https://yosyshq.readthedocs.io/projects/ yosys/en/latest/cmd/index_passes_equiv.html. Accessed Aug. 2025

2025