arxiv: 2605.05496 · v1 · submitted 2026-05-06 · 💻 cs.AR

Recognition: unknown

DICE: Enabling Efficient General-Purpose SIMT Execution with Statically Scheduled Coarse-Grained Reconfigurable Arrays

Jiayi Wang , Ang Da Lu , Zhichen Zeng , Ang Li

Authors on Pith no claims yet

Pith reviewed 2026-05-08 15:25 UTC · model grok-4.3

classification 💻 cs.AR

keywords CGRASIMTGPU architectureenergy efficiencystatic schedulingreconfigurable arraysregister filespatial pipelines

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The pith

A GPU design using statically scheduled coarse-grained reconfigurable arrays achieves 1.77 to 1.90 times better dynamic energy efficiency than conventional SIMD processors while maintaining comparable performance.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper aims to show that the energy waste in GPUs from frequent register file accesses and complex control logic can be greatly reduced by replacing their SIMD execution units with coarse-grained reconfigurable arrays that use static scheduling. Threads are dispatched in a pipelined way so that data flows directly between processing elements instead of being stored and retrieved repeatedly. Dynamic elements like variable memory times or branches are managed by breaking the program into p-graphs that span multiple configurations. Optimizations such as double-buffered memory for quick reconfiguration and a unit to combine memory requests from successive threads help hide overheads. A sympathetic reader would care because this suggests a path to more power-efficient parallel computing hardware that still supports the familiar SIMT programming model without losing speed.

Core claim

DICE replaces the SIMD backend of GPUs with minimal-overhead statically scheduled CGRAs. Active threads are dispatched in pipelined fashion onto the CGRA fabric where data flows directly between PEs to reduce RF accesses for intermediate values. Programs with runtime dynamism are compiled into p-graphs by partitioning dynamic dependence edges across separate configurations. Double-buffered configuration memory hides reconfiguration latency, compile-time unrolling boosts utilization, and a temporal memory coalescing unit merges requests from pipelined threads. On standard benchmarks this cuts register file accesses by 68 percent on average, delivering 1.77-1.90x dynamic energy efficiency and

What carries the argument

The p-graph, which partitions dynamic dependence edges across separate CGRA configurations to support static scheduling for operations with runtime variability such as memory loads and control flow.

If this is right

Register file accesses decrease by 68 percent on average.
CGRA-based processors reach a geometric mean of 1.77-1.90 times the dynamic energy efficiency of conventional streaming multiprocessors.
Average power is reduced by 42.0 to 45.9 percent.
The complete system delivers performance levels similar to those of traditional GPU designs.
Spatial pipeline execution on reconfigurable hardware supports general-purpose SIMT workloads effectively.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

The approach might be adapted to other many-core or accelerator designs facing similar energy bottlenecks from control and storage overhead.
Future work could explore automatic compilation tools that better optimize p-graph partitioning for a wider range of applications.
Physical implementation would allow verification of whether the simulated savings translate to real silicon under varying workloads.
This highlights an opportunity to trade some flexibility in scheduling for lower power in parallel processors.

Load-bearing premise

The performance and energy model used in evaluation correctly captures the behavior of both the baseline SIMD processors and the CGRA-based design, including reconfiguration overheads and memory request merging.

What would settle it

Running the same set of parallel benchmarks on actual hardware built with both the conventional design and the new CGRA approach, using identical computation and memory resources, would falsify the claims if the energy efficiency improvement falls well below 1.5 times or if performance drops significantly.

Figures

Figures reproduced from arXiv: 2605.05496 by Ang Da Lu, Ang Li, Jiayi Wang, Zhichen Zeng.

**Figure 1.** Figure 1: GPGPU SIMD lockstep execution model vs. DICE CGRA thread view at source ↗

**Figure 3.** Figure 3: Control-data flow graph example (LD: Load, BB: Basic block) view at source ↗

**Figure 4.** Figure 4: p-graphs constraints functional (SF) operations according to the arithmetic logic units (ALU) types, with a 1-bit control signal for predicated execution. The interconnect uses statically scheduled, wireswitched routing similar to the one in AHA [23]. A. p-graph formation To support operations with runtime dynamism, including memory operations with unpredictable, variable latency, and data-dependent contr… view at source ↗

**Figure 5.** Figure 5: DICE software flow and hardware execution stages view at source ↗

**Figure 6.** Figure 6: DICE top-level organization. CGRA Processors (CPs) are grouped view at source ↗

**Figure 2.** Figure 2: Operands are read from the register file into the view at source ↗

**Figure 7.** Figure 7: CGRA Processor (CP) microarchitecture scheduled to execute a specific p-graph, DICE instantiates a corresponding execution block, referred to as an e-block. An e-block is a dynamic runtime entity that encapsulates the execution of a p-graph for currently active threads in a given CTA. Conceptually, p-graphs and e-blocks are analogous to static and dynamic instructions, respectively, in conventional CPU/GPG… view at source ↗

**Figure 8.** Figure 8: CGRA Processor (CP) pipeline execution example (M: metadata, B: CGRA bitstream, pg: view at source ↗

**Figure 9.** Figure 9: Normalized RF accesses (%) (DICE vs. RTX2060S) view at source ↗

**Figure 10.** Figure 10: Speedup (×) (DICE variants vs. RTX2060S) 0 20 40 60 80 100 RTX2060S Cycle Breakdown (%) NN BFS-1 BFS-2 BPNN-1 BPNN-2 SC GE-1 GE-2 HS PF Average 0 20 40 60 80 100 DICE Cycle Breakdown (%) Stall Conditions Scoreboard Pipe Stall Idle 0 20 40 60 80 100 Avg. Function Unit Utilization (%) RTX2060S Utilization (max=80%)* All time Stall excluded 14.0 3.5 10.8 11.8 13.2 6.3 5.1 10.1 35.6 29.7 14.5 0 20 40 60 80 10… view at source ↗

**Figure 11.** Figure 11: Cycle breakdown and average functional unit utilization. Top: view at source ↗

**Figure 12.** Figure 12: Energy breakdown of NN benchmark in (a) RTX2060S system (b) view at source ↗

**Figure 13.** Figure 13: Energy & power efficiency (DICE CPs vs. RTX2060S SMs) view at source ↗

**Figure 16.** Figure 16: Speedup (×) of DICE-O48, DICE-O72, and RTX6000 (vs. RTX5000). 0 1 2 3 4 Energy efficiency (×) Energy efficiency (×) NN BFS-1 BFS-2 BPNN-1 BPNN-2 SCGE-1GE-2HS PF GEOMEAN 0 50 100 Power reduction (%) Power reduction (%) (a) DICE-O48 vs. RTX5000 0 1 2 3 4 Energy efficiency (×) Energy efficiency (×) NN BFS-1 BFS-2 BPNN-1 BPNN-2 SCGE-1GE-2HS PF GEOMEAN 0 50 100 Power reduction (%) Power reduction (%) (b) DICE-… view at source ↗

**Figure 17.** Figure 17: Dynamic energy efficiency and power reduction (DICE CPs vs. view at source ↗

**Figure 18.** Figure 18: Speedup (×) and RF Accesses Ratio (%) (DICE-UO vs. RTX3070) effectively by increasing the number of CPs, while maintaining superior energy efficiency and power advantages. 3) Performance Comparison Against Newer GPUs: We additionally compare DICE against the RTX3070. Since each RTX3070 SM offers 2× the FP32 throughput of a Turing SM, we scale DICE both up and out (DICE-UO) to match the RTX3070 compute res… view at source ↗

read the original abstract

While GPUs dominate massively parallel computing through the single-instruction, multiple-thread (SIMT) programming model, their underlying single-instruction, multiple-data (SIMD) execution incurs substantial energy overhead from frequent register file (RF) accesses and complex control logic. We present DICE, a novel architecture that addresses these inefficiencies by replacing the SIMD backend with minimal-overhead, statically scheduled coarse-grained reconfigurable arrays (CGRAs). Unlike SIMD units that execute warps of threads in lockstep, DICE dispatches active threads in a pipelined manner onto the CGRA fabric, where data flow directly between processing elements (PEs), reducing RF accesses for intermediate values. To handle operations with runtime dynamism, such as variable-latency memory loads and data-dependent control flow, while preserving static scheduling, DICE compiles programs into "p-graphs" by partitioning dynamic dependence edges across separate CGRA configurations. DICE further introduces several key optimizations: double-buffered configuration memory to hide reconfiguration latency, compile-time p-graph unrolling to enhance resource utilization, and a temporal memory coalescing unit (TMCU) to merge memory requests from consecutive, pipelined threads. Evaluations on Rodinia benchmarks in Accel-sim demonstrate that DICE reduces register file accesses by 68% on average. With equivalent computation and memory resources, DICE's CGRA Processors (CPs) achieve a geometric mean of 1.77-1.90x dynamic energy efficiency and 42.0%-45.9% average power reduction compared to the modeled NVIDIA Turing Streaming Multiprocessors (SMs), while the full DICE system achieves performance comparable to the modeled Turing GPU baselines. DICE demonstrates that spatial pipeline execution can deliver substantial energy savings without sacrificing performance.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

DICE shows how statically scheduled CGRAs with p-graphs can cut RF accesses and energy in SIMT code, but the 1.8x efficiency numbers rest entirely on unverified Accel-sim extensions.

read the letter

The core idea is to swap out the SIMD execution units in a GPU-style SIMT processor for coarse-grained reconfigurable arrays that run threads in a spatial pipeline. Data moves directly between PEs instead of bouncing through the register file, which the paper claims drops RF accesses by 68%. To keep static scheduling while handling variable-latency loads and branches, they split dynamic edges into p-graphs that span multiple CGRA configurations, plus double-buffered config memory and a temporal coalescing unit for memory requests from pipelined threads. That combination is not a trivial extension of prior CGRA or GPU work and is the part worth paying attention to. The Rodinia results in Accel-sim then show the CGRA processors at 1.77-1.90x dynamic energy efficiency and 42-46% lower power versus a modeled Turing SM, with full-system performance holding up. Those are the concrete numbers the paper delivers. The obvious soft spot is that every quantitative claim comes from cycle-accurate simulation of the new mechanisms with no hardware measurements, no open artifacts, and no cross-check against another energy model. Accel-sim is GPU-oriented, so the modeling choices for p-graph partitioning, reconfiguration overhead, and the TMCU directly drive the reported gains; any mismatch scales the results. The evaluation itself is straightforward and uses standard benchmarks, but the lack of independent validation keeps the confidence low. This paper is for people working on microarchitectural alternatives to conventional SIMT execution and energy efficiency in parallel processors. It has a coherent architecture story and clean-enough evaluation to deserve peer review, even if reviewers will want more evidence on the modeling fidelity.

Referee Report

2 major / 2 minor

Summary. The paper proposes DICE, which replaces SIMD execution in GPUs with statically scheduled CGRAs for SIMT workloads. It introduces p-graphs to partition dynamic dependence edges (e.g., from variable-latency loads and control flow) across configurations while preserving static scheduling, plus optimizations including double-buffered configuration memory, compile-time p-graph unrolling, and a temporal memory coalescing unit (TMCU). Cycle-accurate Accel-sim evaluations on Rodinia benchmarks report 68% average RF access reduction; with equivalent resources, DICE CGRA processors achieve 1.77-1.90x dynamic energy efficiency and 42.0-45.9% power reduction versus modeled NVIDIA Turing SMs, while the full system matches baseline performance.

Significance. If the Accel-sim results hold, DICE offers a concrete path to spatial dataflow execution for general-purpose SIMT codes, with substantial RF and power savings that could inform future GPU microarchitectures in energy-constrained settings. The evaluation uses external Rodinia benchmarks and a third-party simulator without fitted parameters or self-referential predictions, which strengthens credibility. However, the absence of hardware measurements or independent model validation limits immediate adoption.

major comments (2)

[§5 (Evaluation)] §5 (Evaluation): The central quantitative claims (1.77-1.90x energy efficiency, 42-45.9% power reduction, 68% RF reduction) are derived solely from Accel-sim runs that extend the simulator to model p-graphs, double-buffered reconfiguration, and the TMCU. No description is given of how energy models for these novel components were constructed, no cross-validation against McPAT/CACTI or alternative simulators is reported, and no hardware prototype exists. This directly affects the reported gains and must be addressed with additional modeling details or sensitivity analysis.
[§4 (Architecture/Design)] §4 (Architecture/Design, TMCU and p-graph sections): The paper states that the TMCU merges requests from pipelined threads and that p-graph partitioning handles dynamism without sacrificing static scheduling, yet no isolated measurements quantify reconfiguration overhead, coalescing latency, or the fraction of the 68% RF reduction attributable to dataflow versus TMCU. These are load-bearing for the claim that spatial pipelines deliver savings without performance loss.

minor comments (2)

[Abstract] Abstract: The two values in the 1.77-1.90x range are not explained (e.g., different resource configurations or benchmark subsets).
[Throughout] Throughout: Ensure first-use definitions for all acronyms (CGRA, SIMT, TMCU, p-graph) and consistent notation for energy versus power metrics.

Simulated Author's Rebuttal

2 responses · 1 unresolved

We thank the referee for the constructive and detailed feedback on our manuscript. We address each major comment below and will revise the paper to incorporate additional modeling details, experiments, and clarifications as outlined.

read point-by-point responses

Referee: [§5 (Evaluation)] §5 (Evaluation): The central quantitative claims (1.77-1.90x energy efficiency, 42-45.9% power reduction, 68% RF reduction) are derived solely from Accel-sim runs that extend the simulator to model p-graphs, double-buffered reconfiguration, and the TMCU. No description is given of how energy models for these novel components were constructed, no cross-validation against McPAT/CACTI or alternative simulators is reported, and no hardware prototype exists. This directly affects the reported gains and must be addressed with additional modeling details or sensitivity analysis.

Authors: We agree that expanded details on energy modeling are needed to fully support the reported gains. In the revised manuscript, we will add a dedicated subsection in §5 describing how the energy models for p-graphs, double-buffered configuration memory, and the TMCU were constructed as extensions to Accel-sim's existing power models (calibrated to NVIDIA Turing). We will also include sensitivity analysis on key parameters such as reconfiguration energy and memory access costs to demonstrate robustness of the 1.77-1.90x energy efficiency and 42.0-45.9% power reduction results. As this is a simulation-based architectural study using a third-party cycle-accurate simulator and external Rodinia benchmarks, a hardware prototype is beyond the current scope; however, the use of unmodified external benchmarks and a public simulator strengthens credibility of the evaluation. revision: yes
Referee: [§4 (Architecture/Design)] §4 (Architecture/Design, TMCU and p-graph sections): The paper states that the TMCU merges requests from pipelined threads and that p-graph partitioning handles dynamism without sacrificing static scheduling, yet no isolated measurements quantify reconfiguration overhead, coalescing latency, or the fraction of the 68% RF reduction attributable to dataflow versus TMCU. These are load-bearing for the claim that spatial pipelines deliver savings without performance loss.

Authors: We concur that isolating component contributions would strengthen the claims regarding spatial pipeline benefits. In the revision, we will augment §5 with new experiments that: (1) measure and report reconfiguration overhead (showing it is hidden by double-buffering), (2) quantify TMCU coalescing latency, and (3) present an ablation study decomposing the 68% average RF access reduction into portions attributable to CGRA dataflow versus TMCU coalescing. These additions will clarify that the primary savings stem from reduced register file accesses due to direct dataflow while maintaining performance parity with the baseline. revision: yes

standing simulated objections not resolved

Absence of hardware prototype or silicon measurements to validate the Accel-sim energy models and reported gains.

Circularity Check

0 steps flagged

No circularity; results are empirical simulation outputs on external benchmarks

full rationale

The paper presents an architecture (p-graphs, double-buffered reconfiguration, TMCU) and reports quantitative claims exclusively from Accel-sim runs on Rodinia benchmarks. No equations, fitted parameters, or predictions are defined in terms of the target metrics; the energy-efficiency and power numbers are direct simulation outputs rather than reductions by construction. No self-citations are invoked to justify uniqueness or load-bearing premises, and the evaluation uses a third-party simulator plus standard external workloads. This is a conventional empirical comparison with no self-referential steps in the derivation chain.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 2 invented entities

The central claims rest on the fidelity of the Accel-sim energy model and on the effectiveness of two newly introduced mechanisms (p-graphs and TMCU) whose overheads are only characterized in simulation.

axioms (1)

domain assumption The Accel-sim simulator accurately captures dynamic energy, power, and performance for both the baseline Turing SM and the proposed CGRA-based design.
All reported speedups and energy ratios depend on this modeling assumption.

invented entities (2)

p-graphs no independent evidence
purpose: Partition dynamic dependence edges across separate statically scheduled CGRA configurations.
New compile-time abstraction introduced to handle variable-latency memory and data-dependent control flow.
Temporal Memory Coalescing Unit (TMCU) no independent evidence
purpose: Merge memory requests from consecutive pipelined threads.
New hardware unit proposed to improve memory bandwidth utilization under the pipelined dispatch model.

pith-pipeline@v0.9.0 · 5632 in / 1517 out tokens · 83478 ms · 2026-05-08T15:25:00.528441+00:00 · methodology

discussion (0)

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