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arxiv: 2605.06808 · v1 · submitted 2026-05-07 · ⚛️ physics.optics · eess.SP

Recognition: 2 theorem links

· Lean Theorem

A 0.08 pJ/bit 56 GBaud Monolithic Optical Receiver Front End for IMDD Photonic Links

Arjun Khurana, Joel Slaby, Joshua J. Wong, Robert P. Pesch, Stephen E. Ralph

Authors on Pith no claims yet

Pith reviewed 2026-05-11 00:46 UTC · model grok-4.3

classification ⚛️ physics.optics eess.SP
keywords optical receiversilicon photonicsmonolithic integrationlow power consumptionhigh-speed analog front endIMDD photonic linksPAM-4input referred noise
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The pith

A monolithically integrated optical receiver front end achieves 28.9 GHz bandwidth and 0.08 pJ/bit at 56 Gbaud in a silicon photonics platform.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents the design, fabrication, and measurement of a monolithically integrated analog front end for optical receivers targeting intensity modulated direct detect photonic links at 56 Gbaud. Low power consumption and low noise drive a layout-driven design that selects circuit topologies and optimizes transistor unit cell configurations to minimize parasitics. This approach yields wide analog bandwidth and reduced input referred noise while keeping total power low. Post-layout simulations and on-wafer measurements of the fabricated device confirm the performance through DC characteristics, noise analysis, and time-domain eye diagrams for on-off keyed and PAM-4 signals up to 64 GBaud. The result shows that monolithic integration in a silicon photonics platform can deliver the bandwidth, noise, and energy efficiency needed for high-speed transceivers.

Core claim

The post-layout analog front end achieves a 28.9 GHz bandwidth with a low-frequency gain of 61.7 dBΩ while consuming 9.22 mW from a 1.2 V supply, with less than 737 nA RMS integrated input referred noise current and 0.08 pJ/bit energy efficiency; measurements on the fabricated device in the GlobalFoundries Fotonix platform validate DC operation, noise performance, and time-domain behavior to 64 GBaud.

What carries the argument

Monolithically integrated optical receiver analog front end using optimized transistor unit-cell layouts to minimize parasitics within the GlobalFoundries Fotonix silicon photonics platform.

If this is right

  • The receiver supports 56 Gbaud IMDD operation with measured eye diagrams for both OOK and PAM-4 formats up to 64 GBaud.
  • Total power draw remains under 10 mW while meeting the noise and bandwidth targets required for high-speed photonic links.
  • Monolithic integration reduces parasitics compared to discrete designs, enabling the reported energy efficiency of 0.08 pJ/bit.
  • The layout-driven design flow demonstrates how circuit topology and unit-cell choices directly control the achieved analog bandwidth of 28.9 GHz.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Further scaling of this approach could support even higher baud rates if additional parasitic reduction techniques are applied in the same platform.
  • Co-integration with photonic modulators or lasers on the same chip becomes more practical once the electrical front end meets these power and noise budgets.
  • The measured energy efficiency suggests potential system-level savings in data-center interconnects that rely on many parallel 56 Gbaud channels.

Load-bearing premise

The chosen transistor unit-cell layouts and monolithic integration in the silicon photonics platform sufficiently suppress parasitics to deliver the simulated bandwidth and noise performance once fabricated.

What would settle it

A fabricated device measurement showing either bandwidth below 28.9 GHz, integrated input referred noise above 737 nA RMS, or power consumption exceeding 9.22 mW would falsify the performance claims.

Figures

Figures reproduced from arXiv: 2605.06808 by Arjun Khurana, Joel Slaby, Joshua J. Wong, Robert P. Pesch, Stephen E. Ralph.

Figure 2
Figure 2. Figure 2: Schematic diagram of AFE driven by output current of the photodiode (iPD), highlighting the various noise contributions from the TIA (consisting of voltage amplifier A1 and feedback resistor RFB), as well as the subsequent PA and OB (captured together as an effective voltage amplifier A2). The input referred noise current PSD is composed of the feedback resistor thermal current noise and the noise of both … view at source ↗
Figure 4
Figure 4. Figure 4: Block diagram of cascaded Cherry-Hooper amplifier-based PA and OB architecture (a) with single gain stage schematic (b) [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Schematic simulated transfer functions for various stages of the AFE including the TIA core, post amplifier and buffer, and the total response [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗
Figure 7
Figure 7. Figure 7: Schematic of 32 μm wide transistor consisting of 4 parallel transistors each with eight, 1 μm wide fingers (a) and nominal top￾down metallization structure (b) [PITH_FULL_IMAGE:figures/full_fig_p005_7.png] view at source ↗
Figure 9
Figure 9. Figure 9: Block diagram of experimental setup for electrical characterization of the optical receiver (a) and microscope image of the fabricated die with three devices-under-test (b) [PITH_FULL_IMAGE:figures/full_fig_p006_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: The receiver was designed with transistors that utilize a nominal supply voltage of 1 V; however, due to the symmetric nature of the CMOS inverter amplifiers within the TIA, PA and OB, the system can be powered with a VDD ranging from 0.8 V up to 1.2 V. For both the time domain and noise experiments, the system was powered with the 1.2 V. At this operating point, the DC current consumption was measured to… view at source ↗
Figure 10
Figure 10. Figure 10: Measured DC current (left) and computed DC power consumption (right) as a function of supply voltage [PITH_FULL_IMAGE:figures/full_fig_p007_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Measured output noise voltage histogram (a) and the computed receiver sensitivity as a function of Q for an OOK-NRZ signaling scheme (b) [PITH_FULL_IMAGE:figures/full_fig_p007_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Measured eye diagrams at the output of the optical receiver with de-embedding of all external circuitry excluding RF probes and the DUT. Columns from left to right correspond to 32 GBaud (a,b), 56 GBaud (c,d), and 64 GBaud (e,f) respectively, while the top (a,c,e) and bottom (b,d,f) rows are NRZ-OOK and PAM-4 respectively [PITH_FULL_IMAGE:figures/full_fig_p007_12.png] view at source ↗
read the original abstract

We present the design, fabrication, and measurement of a monolithically integrated optical receiver analog front end, where low power operation is a primary consideration with a goal of supporting 56 Gbaud intensity modulated direct detect transceivers. The need for low-power consumption and low-noise operation motivates a monolithic, layout driven design approach which begins with circuit topology selection and analysis. Various transistor unit cell layout configurations are explored, minimizing parasitics, enabling wide analog bandwidth and reduced input referred noise. The post-layout analog front end achieves a 28.9 GHz bandwidth with a low-frequency gain of 61.7 dB{\Omega}. This circuit was designed within the GlobalFoundries FotonixTM monolithic silicon photonics platform. The fabricated device is characterized by its DC operation, noise characteristics, and time domain behavior. The final design was validated by on-off keyed and PAM-4 electrical eye diagram measurements to 64 GBaud, consuming 9.22 mW of power from a 1.2 V supply with less than 737 nA RMS integrated input referred noise current and 0.08 pJ/bit.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The manuscript presents the design, post-layout simulation, fabrication, and experimental characterization of a monolithic optical receiver analog front end in the GlobalFoundries Fotonix silicon photonics platform. It claims a post-layout bandwidth of 28.9 GHz with 61.7 dBΩ gain, and fabricated device performance including DC characteristics, noise, and eye diagrams up to 64 GBaud, with 9.22 mW power consumption from 1.2 V, integrated input-referred noise <737 nA RMS, and energy efficiency of 0.08 pJ/bit at 56 GBaud.

Significance. If the measured results confirm the simulated performance, this work provides a valuable demonstration of low-power, high-speed monolithic photonic receivers enabled by layout optimizations to reduce parasitics. It contributes to the development of efficient IMDD photonic links by achieving competitive energy efficiency and supporting high baud rates.

major comments (2)
  1. [Abstract] Abstract: The post-layout simulation reports 28.9 GHz bandwidth and the fabricated device is said to achieve <737 nA RMS integrated input referred noise current. However, the manuscript does not appear to include a measured frequency response or S21 data to verify that the actual bandwidth in silicon matches the simulated value. Since the integrated noise depends on the effective bandwidth, this comparison is necessary to substantiate the noise performance claim.
  2. [Fabricated device characterization] Fabricated device characterization section: The time-domain eye diagrams validate operation to 64 GBaud, but without a direct sim-to-meas comparison for bandwidth and noise, the assumption that the chosen transistor unit-cell layouts sufficiently suppress parasitics remains the weakest link in supporting the headline metrics of 28.9 GHz bandwidth and <737 nA RMS noise.
minor comments (1)
  1. [Abstract] The abstract states that 'various transistor unit cell layout configurations are explored' but provides no details on the number of configurations tested or the selection criteria for the final design.

Simulated Author's Rebuttal

2 responses · 1 unresolved

We thank the referee for the constructive feedback on our manuscript. We address each major comment below with honest responses and indicate where revisions to the text are feasible.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The post-layout simulation reports 28.9 GHz bandwidth and the fabricated device is said to achieve <737 nA RMS integrated input referred noise current. However, the manuscript does not appear to include a measured frequency response or S21 data to verify that the actual bandwidth in silicon matches the simulated value. Since the integrated noise depends on the effective bandwidth, this comparison is necessary to substantiate the noise performance claim.

    Authors: We agree that a measured S21 frequency response would enable a more direct sim-to-meas comparison of bandwidth. Our experimental focus was on DC characteristics, direct integrated input-referred noise measurements, and time-domain eye diagrams to 64 GBaud, which provide functional validation of the receiver's ability to support the target rates. The reported noise figure is a measured integrated value rather than a simulation-derived quantity. We will revise the abstract and characterization section to explicitly note the lack of S21 data and clarify the measurement approach, but we cannot add measured S21 curves without new experiments. revision: partial

  2. Referee: [Fabricated device characterization] Fabricated device characterization section: The time-domain eye diagrams validate operation to 64 GBaud, but without a direct sim-to-meas comparison for bandwidth and noise, the assumption that the chosen transistor unit-cell layouts sufficiently suppress parasitics remains the weakest link in supporting the headline metrics of 28.9 GHz bandwidth and <737 nA RMS noise.

    Authors: The post-layout simulations include parasitic extraction from the optimized unit-cell layouts. Measured power consumption, noise, and eye quality at high baud rates are consistent with these simulations, indicating that parasitics were adequately controlled. We will expand the discussion in the revised manuscript to better articulate this consistency and the role of the layout choices, while acknowledging the absence of direct bandwidth measurements. revision: partial

standing simulated objections not resolved
  • We do not possess measured S21 or frequency-response data from the fabricated device, preventing a direct sim-to-meas bandwidth comparison.

Circularity Check

0 steps flagged

No circularity: experimental design-and-measurement paper

full rationale

The manuscript presents circuit topology selection, transistor layout exploration for parasitic minimization, post-layout simulation results, fabrication in GlobalFoundries Fotonix, and direct measurements (DC, noise, eye diagrams). No equations, derivations, or predictions are offered that reduce by construction to fitted parameters, self-citations, or ansatzes imported from prior work. Performance numbers (28.9 GHz BW, 61.7 dBΩ gain, 9.22 mW, <737 nA RMS noise, 0.08 pJ/bit) are reported from simulation and measurement without any self-referential loop. The central assumption about parasitic suppression is an engineering claim subject to experimental validation, not a mathematical self-definition.

Axiom & Free-Parameter Ledger

2 free parameters · 2 axioms · 0 invented entities

The design rests on standard analog-circuit small-signal models, foundry-provided device parameters, and post-layout parasitic extraction; no new physical entities are postulated.

free parameters (2)
  • transistor unit cell layout configurations
    Multiple configurations explored and selected to minimize parasitics for target bandwidth and noise.
  • bias currents and transistor sizing
    Chosen during schematic and layout phases to meet power and gain targets.
axioms (2)
  • domain assumption Foundry-provided compact models and parasitic extraction tools accurately predict fabricated circuit behavior
    Invoked for post-layout simulation that guided the final design.
  • standard math Standard small-signal analysis applies to the receiver front-end at the target data rates
    Used to estimate bandwidth and noise from circuit topology.

pith-pipeline@v0.9.0 · 5522 in / 1437 out tokens · 67302 ms · 2026-05-11T00:46:53.010663+00:00 · methodology

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Reference graph

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