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arxiv: 2605.06952 · v1 · submitted 2026-05-07 · 💻 cs.AR

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EDA-Schema-V2: A Multimodal Schema, Open Datasets, and Benchmarks for Machine Learning in Digital Physical Design

Pratik Shrestha , Alec Aversa , Ioannis Savidis
Authors on Pith no claims yet

Pith reviewed 2026-05-11 01:13 UTC · model grok-4.3

classification 💻 cs.AR
keywords EDAmachine learningphysical designdatasetsbenchmarksdigital circuitsOpenROADtiming prediction
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The pith

EDA-Schema-V2 supplies a multimodal schema and large open datasets from the full digital design flow to support machine learning research in physical design.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces an open schema called EDA-Schema-V2 to structure multimodal data for machine learning in digital physical design. It generates large datasets covering the entire flow from synthesis to routing using open benchmarks and tools. By defining twelve prediction tasks and providing baseline results, it aims to create standardized evaluation points for ML methods. This matters because open data can reduce barriers to applying ML to optimize chip layouts for better performance and efficiency.

Core claim

The authors present EDA-Schema-V2 as an open multimodal schema that organizes physical attributes and quality-of-results metrics across logic synthesis, floorplanning, placement, clock network synthesis, and routing. Using SkyWater 130nm, Nangate 45nm, IHP SG13G2 130nm, and ASAP 7nm process design kits with the OpenROAD flow, they generate 7776 design instances from the IWLS'05 benchmark suite through sweeps of clock period, core utilization, and aspect ratio. The resulting collection contains over 275 million gates, 75 million nets, and more than 36 million timing paths. They further identify twelve representative prediction tasks for timing, power, area, and routing metrics, supply initial

What carries the argument

EDA-Schema-V2 is the multimodal schema that supplies structured representations of physical attributes and quality-of-results metrics across the stages of the design flow from logic synthesis through detailed routing.

If this is right

  • Machine learning models can be trained and compared on consistent stage-resolved data spanning synthesis to routing.
  • The public dataset of 7776 instances supplies over 275 million gates and 75 million nets for developing predictors of timing, power, area, and routing.
  • Twelve defined prediction tasks with baseline analyses create standardized points for measuring progress in ML-based physical design methods.
  • Releasing both the schema and the data supports direct reproducibility across different research groups.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If adopted by others, the schema could allow merging datasets across tool flows to create larger combined training collections.
  • Models built on these open instances could be tested for how well they transfer to proprietary industrial netlists.
  • Adding sweeps over additional variables such as cell library choices or power-grid densities would test whether the current parameter space is sufficient.

Load-bearing premise

That datasets generated from the IWLS'05 circuits with the specified open PDKs and OpenROAD parameter sweeps will prove representative for training ML models that generalize to industrial designs and other tools.

What would settle it

Train models on the released dataset and evaluate prediction accuracy on designs produced with a commercial EDA tool or different process technologies; substantially lower accuracy than on the original data would show the benchmarks lack broad utility.

Figures

Figures reproduced from arXiv: 2605.06952 by Alec Aversa, Ioannis Savidis, Pratik Shrestha.

Figure 1
Figure 1. Figure 1: Block representation of the automated physical design flow. [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: EDA-Schema-V2 entity relationship diagram. Entities in yellow represent the Design Flow Hierarchy [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Sample circuit represented as a netlist graph [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Image attributes associated with the netlist entity for the [PITH_FULL_IMAGE:figures/full_fig_p007_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Binary spatial maps associated with the clock network entity for the [PITH_FULL_IMAGE:figures/full_fig_p008_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Image attributes associated with the power delivery network (PDN) entity after the completion of the [PITH_FULL_IMAGE:figures/full_fig_p009_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Timing path graphs 𝑇 𝑃𝐺 extracted from the netlist graph 𝑁 𝐿𝐺 of the circuit shown in [PITH_FULL_IMAGE:figures/full_fig_p009_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Routability metrics represented as scalar-valued RUDY maps at the final design stage for the [PITH_FULL_IMAGE:figures/full_fig_p010_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Distribution of post-routing quality-of-results (QoR) metrics across benchmark circuits for each [PITH_FULL_IMAGE:figures/full_fig_p016_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Analysis of timing-clean and timing-violating path distributions after completion of the final design [PITH_FULL_IMAGE:figures/full_fig_p017_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Distribution of final-stage quality-of-results metrics for total area, total power consumption, worst [PITH_FULL_IMAGE:figures/full_fig_p018_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Distribution of Pearson correlation coefficients between quality-of-results metrics and design param [PITH_FULL_IMAGE:figures/full_fig_p019_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: Change in the distribution of (a) total area, (b) total power, (c) worst slack, (d) total negative slack, (e) [PITH_FULL_IMAGE:figures/full_fig_p020_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: Inter-design stage correlation of QoR and timing metrics across all benchmark circuits in the NG45 [PITH_FULL_IMAGE:figures/full_fig_p027_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: Distribution of final-stage QoR metrics for total area, total power, worst-case slack, total negative [PITH_FULL_IMAGE:figures/full_fig_p032_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: Distribution of Pearson correlation coefficients between QoR metrics and design parameters across [PITH_FULL_IMAGE:figures/full_fig_p033_16.png] view at source ↗
Figure 17
Figure 17. Figure 17: Distribution of final-stage QoR metrics for total area, total power, worst-case slack, total negative [PITH_FULL_IMAGE:figures/full_fig_p033_17.png] view at source ↗
Figure 18
Figure 18. Figure 18: Distribution of Pearson correlation coefficients between QoR metrics and design parameters across [PITH_FULL_IMAGE:figures/full_fig_p034_18.png] view at source ↗
Figure 19
Figure 19. Figure 19: Distribution of final-stage QoR metrics for total area, total power, worst-case slack, total negative [PITH_FULL_IMAGE:figures/full_fig_p034_19.png] view at source ↗
Figure 20
Figure 20. Figure 20: Distribution of Pearson correlation coefficients between QoR metrics and design parameters across all [PITH_FULL_IMAGE:figures/full_fig_p035_20.png] view at source ↗
Figure 21
Figure 21. Figure 21: Change in the distribution of (a) total area, (b) total power, (c) worst slack, (d) total negative slack, (e) [PITH_FULL_IMAGE:figures/full_fig_p035_21.png] view at source ↗
Figure 22
Figure 22. Figure 22: Change in the distribution of (a) total area, (b) total power, (c) worst slack, (d) total negative slack, (e) [PITH_FULL_IMAGE:figures/full_fig_p036_22.png] view at source ↗
Figure 23
Figure 23. Figure 23: Change in the distribution of (a) total area, (b) total power, (c) worst slack, (d) total negative slack, (e) [PITH_FULL_IMAGE:figures/full_fig_p036_23.png] view at source ↗
Figure 24
Figure 24. Figure 24: Inter-design stage correlation of QoR and timing metrics across all benchmark circuits in the SKY130 [PITH_FULL_IMAGE:figures/full_fig_p037_24.png] view at source ↗
Figure 25
Figure 25. Figure 25: Inter-design stage correlation of QoR and timing metrics across all benchmark circuits in the IHP130 [PITH_FULL_IMAGE:figures/full_fig_p038_25.png] view at source ↗
Figure 26
Figure 26. Figure 26: Inter-design stage correlation of QoR and timing metrics across all benchmark circuits in the ASAP7 [PITH_FULL_IMAGE:figures/full_fig_p039_26.png] view at source ↗
read the original abstract

The continuous scaling of CMOS technology has significantly increased the complexity of very large-scale integrated circuits, driving interest in applying machine learning (ML) to electronic design automation (EDA). However, the limited availability of open and standardized datasets limits interoperability, comparability, and reproducibility in ML-based research. This paper introduces EDA-Schema-V2, an open multimodal schema that provides a structured framework for representing and analyzing datasets in digital physical design. The schema includes representations of physical attributes and quality-of-results metrics across multiple stages of the design flow, including logic synthesis, floorplanning, placement, clock network synthesis, and routing. Utilizing the SkyWater 130nm, Nangate 45nm, IHP SG13G2 130nm, and ASAP 7nm open-source process design kits with the OpenROAD tool flow, datasets of physical circuit designs from the IWLS'05 benchmark suite are generated and analyzed. The dataset comprises 7,776 design instances spanning 18 benchmark circuits and includes stage-resolved representations from synthesis through detailed routing, generated through parameter sweeps over clock period, core utilization, and aspect ratio. The dataset contains over 275 million gates, 75 million nets, and more than 36 million extracted timing paths. In addition, twelve representative prediction tasks spanning timing, power, area, and routing metrics are identified, along with baseline analyses that characterize stage-to-stage predictability across the design flow. The resulting datasets and baselines are publicly released to support reproducible ML research and establish standardized benchmarks for evaluating ML-based approaches in digital physical design.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 1 minor

Summary. The manuscript introduces EDA-Schema-V2, a multimodal schema for representing physical attributes and QoR metrics across the digital physical design flow (synthesis through routing). It generates and releases a dataset of 7,776 instances from the 18 IWLS'05 circuits using SkyWater 130nm, Nangate 45nm, IHP SG13G2 130nm, and ASAP 7nm PDKs with OpenROAD, via sweeps over clock period, core utilization, and aspect ratio. The data includes stage-resolved representations, over 275 million gates, 75 million nets, and 36 million timing paths. Twelve prediction tasks (timing, power, area, routing) are defined with stage-to-stage baseline analyses, and all artifacts are publicly released to support reproducible ML research and standardized benchmarks.

Significance. If the released schema and datasets see adoption, the work could meaningfully advance reproducible ML-for-EDA research by supplying the first large-scale, open, stage-resolved multimodal resource spanning the full physical design flow. The scale of the generated data and the explicit baseline characterizations for cross-stage predictability are concrete strengths that lower the barrier for model development and comparison. The contribution is primarily infrastructural rather than algorithmic, but the open release directly addresses a documented community need.

major comments (1)
  1. [Abstract] Abstract: The central claim that the datasets and baselines 'establish standardized benchmarks for evaluating ML-based approaches in digital physical design' is load-bearing for the paper's stated contribution. This claim rests on an unverified assumption of representativeness; the generation pipeline is confined to IWLS'05 circuits, four specific open PDKs, and OpenROAD parameter sweeps, with no described cross-tool, cross-PDK, or cross-scale validation to show that timing/power/area distributions or netlist statistics remain predictive outside this regime.
minor comments (1)
  1. The abstract and introduction would benefit from an explicit statement of the schema's concrete data formats or serialization (e.g., how physical attributes and per-stage QoR metrics are encoded) to improve immediate usability for readers intending to adopt the schema.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the constructive feedback and positive assessment of the work's potential to advance reproducible ML-for-EDA research. We address the major comment regarding the benchmark claim in the abstract.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The central claim that the datasets and baselines 'establish standardized benchmarks for evaluating ML-based approaches in digital physical design' is load-bearing for the paper's stated contribution. This claim rests on an unverified assumption of representativeness; the generation pipeline is confined to IWLS'05 circuits, four specific open PDKs, and OpenROAD parameter sweeps, with no described cross-tool, cross-PDK, or cross-scale validation to show that timing/power/area distributions or netlist statistics remain predictive outside this regime.

    Authors: We agree that the datasets are generated from a specific set of 18 IWLS'05 circuits, four open PDKs, and OpenROAD sweeps, without cross-tool or cross-scale validation to demonstrate broader representativeness. The manuscript does not assert that the timing, power, or area distributions are predictive outside this regime. The core contribution is the release of the first large-scale, open, stage-resolved multimodal schema and dataset spanning synthesis through routing, together with twelve explicitly defined prediction tasks and baseline results. To address the concern, we will revise the abstract to state that the work 'provides open datasets, a multimodal schema, and baselines that contribute to standardized benchmarks' rather than 'establish standardized benchmarks'. We will also add a short paragraph in the conclusions acknowledging the current scope limitations and encouraging community extensions to other tools and PDKs. This change ensures the claim accurately reflects the evidence while preserving the infrastructural value of the public release. revision: yes

Circularity Check

0 steps flagged

No circularity: data-generation and release effort with independent process description

full rationale

The paper introduces a schema, generates datasets via explicit parameter sweeps on IWLS'05 circuits with open PDKs and OpenROAD, identifies 12 prediction tasks, and releases the data plus baseline characterizations. No equations, fitted parameters renamed as predictions, self-citations used as load-bearing uniqueness theorems, or ansatzes smuggled in via prior work appear in the provided text. All claims rest on the described generation pipeline and public release rather than any reduction to inputs by construction.

Axiom & Free-Parameter Ledger

3 free parameters · 1 axioms · 1 invented entities

The contribution rests on the new schema definition and the data-generation pipeline; no free parameters are fitted to achieve a target result, only swept for coverage.

free parameters (3)
  • clock period
    Swept across values to produce varied timing scenarios in the dataset generation
  • core utilization
    Swept across values to produce varied area scenarios in the dataset generation
  • aspect ratio
    Swept across values to produce varied shape scenarios in the dataset generation
axioms (1)
  • domain assumption OpenROAD flow with the listed open PDKs produces valid, extractable physical designs for IWLS'05 benchmarks
    Invoked to justify the generated dataset as representative of real design flow outputs
invented entities (1)
  • EDA-Schema-V2 no independent evidence
    purpose: Multimodal structured representation of physical design attributes and QoR metrics across design stages
    Newly defined framework whose adoption is the primary contribution

pith-pipeline@v0.9.0 · 5591 in / 1449 out tokens · 38589 ms · 2026-05-11T01:13:24.618351+00:00 · methodology

discussion (0)

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Reference graph

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