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arxiv: 2605.11261 · v1 · submitted 2026-05-11 · 📡 eess.SY · cs.SY

Recognition: 2 theorem links

· Lean Theorem

236 {μ}W Direct-RF PLL-Free Multi-PSK Transmitter Using Oscillator-Based Phase Synthesis

Dong S. Ha, Fariborz Lohiri Pour, Jeffrey S. Walling, Meysam Sohani Darban

Pith reviewed 2026-05-13 01:29 UTC · model grok-4.3

classification 📡 eess.SY cs.SY
keywords direct RF transmitterPLL-freemulti-PSKring oscillatorphase synthesislow powercharge extraction2.4 GHz
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The pith

Ring oscillator performs direct multi-PSK modulation at 2.4 GHz by synchronized charge extraction without PLL.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper demonstrates a transmitter architecture that induces controlled phase shifts directly in a ring oscillator for various PSK schemes. By extracting charge at precise transition points and using multi-triggering, it maintains constant amplitude and frequency. This eliminates the PLL, reducing power to 236 μW and size to a tiny core area while achieving acceptable EVM at 2 MSps. Such a design matters for battery-powered wireless devices where simplicity and efficiency are key.

Core claim

The proposed direct-RF multi-PSK transmitter eliminates the PLL by performing phase modulation within a ring oscillator using synchronized charge extraction at transition points to induce controlled phase shifts while maintaining constant amplitude and frequency. A time-domain multi-triggering technique enables reconfigurable support for 16-PSK, 8-PSK, QPSK, and BPSK in a unified structure, fabricated in 22-nm FD-SOI at 2.4 GHz with 2 MSps symbol rate and 5.13% rms EVM.

What carries the argument

Synchronized charge extraction at the oscillator transition points combined with time-domain multi-triggering, which induces precise phase shifts in the ring oscillator for multi-mode PSK modulation.

If this is right

  • The core transmitter consumes only 236 μW while delivering -10 dBm output over 60 MHz bandwidth.
  • Multiple PSK modes are supported in a single hardware structure without additional circuits.
  • The design occupies an extremely small area of 23 × 17.6 μm² in 22-nm process.
  • Symbol rate of 2 MSps is achieved with maximum EVM of 5.13% rms in ISM band.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • This method could simplify integration in highly scaled CMOS processes for IoT sensors.
  • Extending the charge extraction technique might allow for higher-order modulations or different frequencies.
  • Absence of PLL may reduce startup time and phase noise issues in some applications.

Load-bearing premise

That synchronized charge extraction at the oscillator transition points can produce precise, repeatable phase shifts for all supported PSK modes while keeping amplitude and frequency constant without post-fabrication calibration or additional compensation circuits.

What would settle it

If repeated measurements show that phase shifts vary beyond the tolerance needed for 5.13% EVM across different PSK modes or under varying supply voltages, the claim of reliable PLL-free operation would be disproven.

Figures

Figures reproduced from arXiv: 2605.11261 by Dong S. Ha, Fariborz Lohiri Pour, Jeffrey S. Walling, Meysam Sohani Darban.

Figure 1
Figure 1. Figure 1: Charge injection effect at different moments of an oscillator’s output. [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Concept of charge extraction on a ring oscillator. [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 4
Figure 4. Figure 4: When the TP window turns on the M1 switch, it connects the Cdis to the Vo[n] and draws a portion of its charge while it tries to raise Vo[n] to VDD, leading to a [PITH_FULL_IMAGE:figures/full_fig_p002_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Chip photograph and the layout of the proposed TX. [PITH_FULL_IMAGE:figures/full_fig_p003_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Measured output spectrum. The absence of a continuous reference frequency is ar￾chitecturally justified by the well-established philosophy of asymmetric complexity, which shifts the synchronization bur￾den to the receiver and prioritizes extreme energy efficiency and a minimal die area for the TX. With direct time-domain phase modulation of the oscillator via synchronous charge extracting, this design avoi… view at source ↗
Figure 7
Figure 7. Figure 7: TX’s constellations for (a) 16DPSK, (b) 8DPSK, (c) QDPSK, and (d) [PITH_FULL_IMAGE:figures/full_fig_p004_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: (a) Measured output matching performance, and (b) power breakdown. [PITH_FULL_IMAGE:figures/full_fig_p004_8.png] view at source ↗
read the original abstract

This paper presents a compact, low-power, direct RF multi-phase-shift keying (PSK) transmitter (TX) that eliminates the need for a phase-locked loop (PLL) by performing phase modulation directly within a ring oscillator. The proposed architecture exploits synchronized charge extraction at the oscillator's transition points to induce controlled phase shifts while maintaining constant amplitude and frequency. A time-domain multi-triggering technique is introduced to enable reconfigurable multi-mode modulation, supporting 16-PSK, 8-PSK, QPSK, and BPSK within a unified hardware structure. The TX circuit is fabricated in a 22-nm FD-SOI process and operates in the ISM band at 2.4 GHz. Measurement results indicate a symbol rate of 2 MSps with a maximum error vector magnitude (EVM) of 5.13% rms. The core TX occupies 23 {\times} 17.6 {\mu}m2 and consumes 236 {\mu}W, excluding the output driver, which delivers -10 dBm output power over a 60 MHz bandwidth. The proposed design achieves a favorable trade-off between power consumption, circuit complexity, and modulation flexibility, making it well-suited for low-power wireless applications.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The paper proposes a direct-RF multi-PSK transmitter that performs phase modulation directly in a ring oscillator using synchronized charge extraction at transition points, eliminating the need for a PLL. It introduces a time-domain multi-triggering technique for reconfigurable BPSK, QPSK, 8-PSK, and 16-PSK modulation. The design is fabricated in 22-nm FD-SOI process, operating at 2.4 GHz ISM band, with measured symbol rate of 2 MSps, maximum EVM of 5.13% rms, core area of 23 × 17.6 μm², and power consumption of 236 μW (excluding output driver delivering -10 dBm over 60 MHz bandwidth).

Significance. Should the measured performance prove robust and reproducible, this architecture offers a significant advancement in ultra-low-power wireless transmitters by achieving multi-level PSK modulation with minimal power and area overhead, bypassing traditional PLL-based frequency synthesis. This could enable more efficient designs for battery-constrained devices in the ISM band.

major comments (2)
  1. [Measurement Results] The EVM measurement of 5.13% rms is reported without accompanying error bars, statistical data from multiple samples, or a full description of the test setup and environmental conditions, which is critical to validate the claim that phase shifts are precise and repeatable without calibration.
  2. [Proposed Architecture] The assertion that synchronized charge extraction maintains constant amplitude and instantaneous frequency while inducing exact phase shifts for all PSK modes lacks supporting analysis or simulation results on the impact of supply noise, temperature drift, and device mismatch in the 22-nm FD-SOI process.
minor comments (2)
  1. [Abstract] The abstract mentions 'favorable trade-off' but does not quantify comparisons to prior art in terms of power or area.
  2. The manuscript would benefit from including detailed schematics of the oscillator and charge extraction circuit to allow better understanding of the phase synthesis mechanism.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the thorough review and valuable comments on our manuscript. We address each major comment below with point-by-point responses and indicate the revisions we will make to strengthen the paper.

read point-by-point responses

  1. Referee: [Measurement Results] The EVM measurement of 5.13% rms is reported without accompanying error bars, statistical data from multiple samples, or a full description of the test setup and environmental conditions, which is critical to validate the claim that phase shifts are precise and repeatable without calibration.

    Authors: We agree that a more complete description of the measurement conditions is important for validating the results. In the revised manuscript, we will add a detailed subsection on the test setup, including the instrumentation (e.g., signal generator, spectrum analyzer, oscilloscope), cabling, power supply configuration, and environmental conditions (controlled room temperature and stable 1.0 V supply). The reported EVM value was obtained from a single fabricated die under these stable conditions, with repeated measurements showing consistent results across modulation modes; we will explicitly state this limitation and note that error bars were omitted because observed variations were negligible. This clarification supports the repeatability claim without calibration. revision: partial

  2. Referee: [Proposed Architecture] The assertion that synchronized charge extraction maintains constant amplitude and instantaneous frequency while inducing exact phase shifts for all PSK modes lacks supporting analysis or simulation results on the impact of supply noise, temperature drift, and device mismatch in the 22-nm FD-SOI process.

    Authors: The original manuscript presents nominal-condition simulations of the phase-shift mechanism. To address the concern, the revised version will include additional post-layout simulations that incorporate supply voltage noise (±10% variation), temperature sweeps from 0 °C to 80 °C, and Monte Carlo analysis for device mismatch and process corners specific to the 22-nm FD-SOI technology. These results will quantify the impact on amplitude stability, instantaneous frequency, and phase accuracy, confirming that the targeted EVM performance is maintained without calibration. revision: yes

Circularity Check

0 steps flagged

No circularity; central claims rest on fabricated-chip measurements, not looped derivations

full rationale

The paper describes a ring-oscillator-based phase-synthesis TX architecture that uses synchronized charge extraction and a time-domain multi-triggering technique to support multi-PSK modes. All reported performance numbers (2 MSps symbol rate, 5.13 % rms EVM, 236 μW core power, 23 × 17.6 μm² area, -10 dBm output) are obtained from direct silicon measurements on a 22 nm FD-SOI die. No equations, fitted parameters, or self-citations are invoked to derive these quantities; the architecture is presented as a circuit solution whose correctness is established empirically rather than by any self-referential mathematical chain. The derivation therefore remains self-contained against external hardware benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 2 axioms · 0 invented entities

The design rests on standard CMOS device physics and ring-oscillator behavior; no new physical entities are introduced and no parameters appear to be fitted to the final performance numbers in the abstract.

axioms (2)
  • domain assumption Ring-oscillator frequency and amplitude remain constant when controlled charge is extracted at transition points.
    Invoked to justify that phase shifts can be applied without disturbing the carrier.
  • standard math Standard 22-nm FD-SOI CMOS device models accurately predict the fabricated circuit behavior.
    Underlying assumption for expecting measured results to match design intent.

pith-pipeline@v0.9.0 · 5537 in / 1496 out tokens · 54296 ms · 2026-05-13T01:29:45.075876+00:00 · methodology

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Lean theorems connected to this paper

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Reference graph

Works this paper leans on

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