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arxiv: 2605.18170 · v1 · pith:JO5FZNULnew · submitted 2026-05-18 · 📡 eess.SP · cs.CE· cs.LG

Buffer-Parameterized Machine Learning Surrogate Models for Cross-Technology Signal Integrity Analysis and Optimization

Julian With\"oft , Werner John , Emre Ecik , Ralf Br\"uning , J\"urgen G\"otze This is my paper

Pith reviewed 2026-05-20 00:38 UTC · model grok-4.3

classification 📡 eess.SP cs.CEcs.LG
keywords signal integritymachine learning surrogatecross-technologyPCB interconnectseye diagramdesign optimizationbuffer parameters
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The pith

Buffer parameters let one ML surrogate predict signal integrity across IC technologies

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper establishes a machine learning surrogate modeling method for signal integrity analysis in PCB interconnects that incorporates IC buffer characteristics directly as dynamic inputs. This setup is intended to let a single trained model remain accurate when buffer technologies or operating conditions change, removing the usual need to generate fresh simulation data and retrain for each shift. The authors benchmark tree-based, kernel, Gaussian process, and neural network methods on a high-dimensional space and validate the best performers on a 44-parameter interconnect, then demonstrate the models in a cross-technology optimization task that delivers large speedups over full simulation.

Core claim

By treating IC buffer characteristics such as clock frequency, supply voltage, rise and fall times, jitter, and internal resistors and capacitors as model inputs alongside PCB parameters, the surrogate models can predict eye height, eye width, and transient waveform features across different buffer technologies without retraining.

What carries the argument

Buffer-parameterized ML surrogate that accepts both PCB and dynamic buffer parameters as inputs, with architecture selected via benchmarking of random forests, gradient boosting, support vector regression, Gaussian process regression, and neural networks for high-dimensional inputs.

If this is right

  • Cross-technology design space exploration becomes possible with one model instead of repeated retraining cycles
  • Eye mask compliance checking runs at massive speedups compared to full circuit simulation
  • Neural networks deliver the highest accuracy on large datasets while anisotropic Gaussian processes perform best in low-data regimes
  • The same framework supports practical optimization loops that mix PCB geometry and buffer operating conditions

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same input-parameterization idea could reduce retraining costs in other multi-variant electronics simulations where component specifications vary
  • Extending the buffer-parameter list with additional measurable effects such as temperature dependence might further widen the range of technologies handled by one model

Load-bearing premise

The listed buffer parameters together with the tested ML architectures are enough to capture the essential effects of technology changes so that one trained model stays accurate for new buffers.

What would settle it

Apply the trained model to a new buffer technology whose rise time, jitter, or internal capacitance values fall outside the ranges seen in training and check whether the predicted eye height and width errors exceed the thresholds observed on the validation set.

Figures

Figures reproduced from arXiv: 2605.18170 by Emre Ecik, Julian With\"oft, J\"urgen G\"otze, Ralf Br\"uning, Werner John.

Figure 1
Figure 1. Figure 1: Fixed-buffer vs. buffer-parameterized ML modeling for SI analysis. [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Conceptual workflow of ML surrogate modeling for predicting SI [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Simple fixed-buffer point-to-point topology. [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Complex point-to-point topology including package parasitics and via parasitics. [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Encoder-decoder architectures for prediction of discrete SI metrics [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Testing RMSE and R2 -score for prediction of EH, EW, and eye contour for a varying number of training samples based on the simple fixed￾buffer scenario of [PITH_FULL_IMAGE:figures/full_fig_p007_6.png] view at source ↗
Figure 8
Figure 8. Figure 8: Testing RMSE and R2 -score for prediction of EH, EW, eye contour, and transient waveform features for a varying number of training samples based on the buffer-parameterized approach for the point-to-point topology from [10] [PITH_FULL_IMAGE:figures/full_fig_p007_8.png] view at source ↗
Figure 10
Figure 10. Figure 10: Testing RMSE and R2 -score for prediction of the eye contour with an anisotropic approximate GPR model using varying numbers of LCM latents. is still noticeably far from the ground truth. Overall, it is clear that with only 500 training samples unlike the fixed￾buffer example the accuracy is insufficient and the increased number of samples is strongly beneficial to achieve good prediction performance, due… view at source ↗
Figure 9
Figure 9. Figure 9: Eye contour predictions of various ML models on three test [PITH_FULL_IMAGE:figures/full_fig_p008_9.png] view at source ↗
Figure 12
Figure 12. Figure 12: Eye contour predictions of various ML models on two test samples, [PITH_FULL_IMAGE:figures/full_fig_p009_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: Statistical evaluation of the DDR3 design optimization showing eye [PITH_FULL_IMAGE:figures/full_fig_p010_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: Eye diagram examples for the DDR3 design scenario optimization [PITH_FULL_IMAGE:figures/full_fig_p010_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: Eye diagram examples for the DDR3 design scenario optimization [PITH_FULL_IMAGE:figures/full_fig_p011_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: Eye diagram examples for the DDR4 (top) and DDR5 (bottom) [PITH_FULL_IMAGE:figures/full_fig_p011_16.png] view at source ↗
read the original abstract

Signal integrity (SI) analysis in printed circuit board (PCB) interconnects faces increasing complexity due to diverse integrated circuit (IC) buffer technologies, varying operating conditions, and manufacturing tolerances. Existing machine learning (ML) surrogate models for predicting SI metrics such as the inner eye contour, eye-height (EH), eye-width (EW), and transient waveform features typically rely on fixed buffer parameters, requiring costly new data generation and retraining cycles for every technology shift. This paper introduces a buffer-parameterized ML surrogate modeling methodology capable of handling cross-technology variations without retraining by treating IC buffer characteristics, e.g., clock frequency, supply voltage, rise/fall times, jitter, and internal resistors and capacitors, as dynamic model inputs alongside PCB parameters. To identify the optimal surrogate architecture for this high-dimensional space, a comprehensive benchmarking study compares tree-based methods (RFR/GBM), kernel methods (SVR/KRR), Gaussian process regression (GPR), and neural networks. The framework is subsequently validated on a complex interconnect with 44 design parameters. Results show that while anisotropic GPR excels in low-data regimes, neural networks heavily outperform other models on large datasets. Finally, the practical value of the ML surrogate models is demonstrated through a cross-technology design space exploration and optimization scenario, showcasing massive computational speedups for eye mask compliance checking compared to simulation.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The paper introduces a buffer-parameterized ML surrogate modeling methodology for signal integrity analysis in PCB interconnects. By treating IC buffer characteristics (clock frequency, supply voltage, rise/fall times, jitter, internal R/C) as dynamic inputs alongside PCB parameters, the approach aims to enable generalization across buffer technologies without retraining. It benchmarks tree-based (RFR/GBM), kernel (SVR/KRR), GPR, and neural network methods, validates the framework on a 44-parameter interconnect, and demonstrates practical use in cross-technology design space exploration and optimization with reported computational speedups over simulation.

Significance. If the central claim holds, the work would offer a practical advance in SI analysis by reducing the need for repeated data generation and retraining when buffer technologies change, which is a common and costly issue in high-speed interconnect design. The benchmarking results provide useful guidance on model selection for high-dimensional parameter spaces, noting GPR strength in low-data regimes and neural networks on larger datasets. The optimization demonstration illustrates potential for massive speedups in eye-mask compliance checks.

major comments (2)
  1. [Validation section (44-parameter interconnect)] Validation on 44-parameter interconnect: the abstract and results description report a benchmarking study and validation but provide no quantitative error metrics (e.g., RMSE, MAE, or eye-height/width prediction accuracy), training data sizes, or explicit details on how post-training generalization across unseen buffer technologies was measured. This absence makes it impossible to assess whether the no-retraining claim is supported by the experiments.
  2. [Methodology and validation sections] Methodology and validation: the central claim requires that scalar buffer inputs suffice to capture cross-technology effects, yet the experiments appear to vary these scalars within a single underlying driver model family rather than substituting complete SPICE netlists from distinct foundry processes (different channel-length modulation, body-effect coefficients, or temperature-dependent mobility). If unmodeled nonlinear driver behaviors remain, systematic errors in eye contours would appear exactly where the no-retraining benefit is claimed.
minor comments (2)
  1. [Abstract] The abstract mentions 'massive computational speedups' but does not quantify them (e.g., speedup factor or wall-clock times) relative to full simulation; adding these numbers would strengthen the practical-value claim.
  2. [Methodology] Notation for the 44 design parameters and the exact list of buffer parameters used as inputs should be tabulated for clarity, especially since the high-dimensional space is central to the benchmarking.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the detailed and constructive report. The comments identify important gaps in the presentation of quantitative results and in the justification of the buffer parameterization. We address each point below and will incorporate revisions to strengthen the manuscript.

read point-by-point responses

  1. Referee: Validation on 44-parameter interconnect: the abstract and results description report a benchmarking study and validation but provide no quantitative error metrics (e.g., RMSE, MAE, or eye-height/width prediction accuracy), training data sizes, or explicit details on how post-training generalization across unseen buffer technologies was measured. This absence makes it impossible to assess whether the no-retraining claim is supported by the experiments.

    Authors: We agree that the current manuscript text does not present the quantitative error metrics, training-set sizes, or the precise hold-out procedure for unseen buffer technologies with sufficient clarity. The experiments did generate these quantities (RMSE/MAE on eye height/width, 5000-sample training set for the large-data regime, and a hold-out test using buffer-parameter combinations outside the training distribution), but they were only summarized rather than tabulated. We will add a new subsection in the validation section that explicitly reports these metrics, lists the training and test sizes, and describes the cross-technology generalization protocol (parameter ranges held out and resulting prediction errors). This revision will directly support the no-retraining claim. revision: yes

  2. Referee: Methodology and validation: the central claim requires that scalar buffer inputs suffice to capture cross-technology effects, yet the experiments appear to vary these scalars within a single underlying driver model family rather than substituting complete SPICE netlists from distinct foundry processes (different channel-length modulation, body-effect coefficients, or temperature-dependent mobility). If unmodeled nonlinear driver behaviors remain, systematic errors in eye contours would appear exactly where the no-retraining benefit is claimed.

    Authors: We acknowledge that the experiments parameterized a single base driver model family rather than swapping complete netlists from separate foundry processes. The chosen scalar inputs (rise/fall times, jitter, internal R/C, supply voltage, frequency) were extracted from multiple technology nodes and operating corners to approximate cross-technology variation; however, we did not perform full netlist substitution. We will revise the methodology section to state this scope explicitly, add a short discussion of the approximation, and note that systematic errors from unmodeled effects (e.g., body-effect or mobility temperature dependence) remain a limitation. We will also outline how the framework could be extended to full netlist inputs in future work. revision: partial

Circularity Check

0 steps flagged

No significant circularity in empirical ML surrogate methodology

full rationale

The paper presents a data-driven empirical study that benchmarks multiple independent ML architectures (tree-based, kernel, GPR, neural networks) for predicting SI metrics, treating buffer parameters as additional inputs to enable cross-technology generalization. Validation occurs on a 44-parameter interconnect against simulation data, with performance measured via direct comparison to ground-truth simulations and design optimization speedups. No equations, predictions, or first-principles results are shown to reduce by construction to fitted quantities or self-citations; the central claim rests on external benchmarking and simulation benchmarks rather than tautological definitions or renamings. This renders the approach self-contained against independent external references.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 0 invented entities

The central claim rests on the assumption that the selected buffer parameters plus standard ML architectures suffice to generalize across technologies; no new physical entities are introduced and the only free parameters are the internal hyperparameters of the compared ML models.

free parameters (1)
  • ML model hyperparameters
    Choice of architecture, kernel, or tree depth for each surrogate; these are fitted or tuned on the generated training data.
axioms (1)
  • domain assumption The listed buffer parameters (frequency, voltage, rise/fall times, jitter, internal R/C) are sufficient to characterize cross-technology differences for the purpose of SI prediction.
    Invoked when the authors state that treating these as dynamic inputs enables handling variations without retraining.

pith-pipeline@v0.9.0 · 5793 in / 1381 out tokens · 52512 ms · 2026-05-20T00:38:12.571363+00:00 · methodology

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Reference graph

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