pith. sign in

arxiv: 2606.16143 · v1 · pith:C5NPCKDBnew · submitted 2026-06-15 · 💻 cs.AR

AIA: A Customized Multi-core RISC-V SoC for Discrete Sampling Workloads in 16 nm

Shirui Zhao , Nimish Shah , Wannes Meert , Marian Verhelst This is my paper

Pith reviewed 2026-06-27 03:00 UTC · model grok-4.3

classification 💻 cs.AR
keywords RISC-V SoCMCMC samplingapproximate inferenceKnuth-Yao samplingmulti-core architectureedge computingprobabilistic modelscustom instructions
0
0 comments X

The pith

A 16 nm RISC-V SoC with 16 custom cores accelerates approximate inference by reducing data movement in MCMC sampling.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces AIA, a multi-core RISC-V system-on-chip fabricated in 16 nm technology to handle computationally expensive Markov Chain Monte Carlo sampling for probabilistic models. It combines a host processor for communication with a two-dimensional mesh of 16 specialized cores that include custom instructions for Knuth-Yao sampling and non-linear function interpolation. Direct access to neighboring cores' register files minimizes data movement, while a dedicated compiler maps and schedules workloads across the cores. This setup targets efficient execution of sampling methods that are difficult to parallelize on conventional processors, aiming to bring robust reasoning capabilities to edge devices.

Core claim

AIA is a fabricated System-on-Chip that uses a RISC-V host processor to handle chip-to-chip communication and a 2D mesh of 16 custom RISC-V cores, each equipped with dedicated instructions and hardware for non-normalized Knuth-Yao sampling, interpolation of functions like logarithms and exponentials, and direct register file access to adjacent cores. A specialized compile chain supports spatial mapping and scheduling to leverage parallelism in MCMC algorithms for approximate inference.

What carries the argument

2D mesh of 16 custom RISC-V cores with custom instructions for non-normalized Knuth-Yao sampling, non-linear function interpolation, and direct neighbor register-file access

Load-bearing premise

The custom instructions for sampling and interpolation together with neighbor register access and the compile chain will deliver substantial reductions in data movement and compute cost for MCMC workloads.

What would settle it

Running a representative MCMC algorithm on the fabricated AIA chip and comparing its energy consumption and execution time against a standard multi-core RISC-V processor without the custom features.

Figures

Figures reproduced from arXiv: 2606.16143 by Marian Verhelst, Nimish Shah, Shirui Zhao, Wannes Meert.

Figure 1
Figure 1. Figure 1: This figure provides an illustrative breakdown of RV-level paralleliza [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: (a) Runtime characterization of different benchmarking workloads, highlighting the diverse operations necessary for probability distribution computation, with sampling identified as the critical operation. (b) Roofline model analysis conducted on an Intel i7-7800X CPU @ 3.50GHz, demonstrating that Gibbs sampling is memory-bound. This suggests the need for a custom accelerator with improved data transfer an… view at source ↗
Figure 3
Figure 3. Figure 3: (a) The architecture of accelerator core. The ALU, multiplication, and dot-product unit of the baseline [PITH_FULL_IMAGE:figures/full_fig_p006_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: The AIA architecture with 16 accelerator cores. [PITH_FULL_IMAGE:figures/full_fig_p006_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: (a) The proposed rejection-based KY sampler hardware architecture. (b) DDG tree for uniform distribution: Pi = 1/3 and the formal to compute the rejection item as shown in the preprocess submodule. (c) Reconfigurable decoder architecture for different precision of n[i]. (d) The signal waveform when random bits from LFSR is 0010. If the first sample result is a rejection, then the FSM will control the hardw… view at source ↗
Figure 6
Figure 6. Figure 6: (a) A toy example to show how to access neighbors’ shared RF. (b) Pseudo-assembly code for the ISA without (W/o) and with (W/) neighboring RF access. (c) With this feature, the memory access pattern can be reduced by 3× for a real-world MRF application. B. Enlarged RF MCMC frequently requires access to its neighbor RVs, hence benefiting from a 2D mesh architecture for data com￾munication between processing… view at source ↗
Figure 7
Figure 7. Figure 7: Interpolation unit to simplify the exp operation. [PITH_FULL_IMAGE:figures/full_fig_p009_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Customized compiler chain for AIA: consists of graph coloring to detect RV-level parallelism, graph mapping to map the RVs on different cores, and [PITH_FULL_IMAGE:figures/full_fig_p010_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Graph coloring result for irregular Bayesian Networks. The Pie graph shows how many nodes have the same color. The line graph indicates the potential throughput gain on different sizes of parallel cores. of PMs. In our work, we used 32-bit fixed-point computing with 1-bit signed, 8-bit integer, and 23-bit fraction, following in the low-precision quantization configuration in [17], [13], which shown with ne… view at source ↗
Figure 11
Figure 11. Figure 11: Peak-performance scaling with voltage and entropy. [PITH_FULL_IMAGE:figures/full_fig_p011_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Throughput performance gains over baseline design and introduced hardware modules. cancer alarm insurance water hailfinder hepar2 link pigs Penguin Art 0 1 2 3 4 5 6 7 8 Energy Efficiency (GSample/s/W) Bayes Nets MRF 1.1x 3.1x 2.0x 2.9x 2.3x 1.7x 4.9x 5.0x 1.4x 0.0x This work PULP baseline: 16 RI5CY SotA: MSSE [PITH_FULL_IMAGE:figures/full_fig_p012_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: Throughput and energy performance compassion on real-world [PITH_FULL_IMAGE:figures/full_fig_p012_13.png] view at source ↗
read the original abstract

Probabilistic models (PMs) are essential in advancing machine learning capabilities, particularly in safety-critical applications involving reasoning and decision-making. Among the methods employed for inference in these models, sampling-based Markov Chain Monte Carlo (MCMC) techniques are widely used. However, MCMC methods come with significant computational costs and are inherently challenging to parallelize, resulting in inefficient execution on conventional CPU/GPU platforms. To overcome these challenges, this paper presents AIA, a multi-core RISC-V System-on-Chip (SoC) design fabricated using Intel's 16 nm process technology. Our Approximate Inference Accelerator (AIA) is specifically designed to empower edge devices with robust decision-making and reasoning abilities. The AIA architecture incorporates a RISC-V host processor to manage chip-to-chip data communication and a 2D mesh of 16 custom versatile RISC-V cores optimized for high-efficiency approximate inference. Each core features (i) custom instructions and datapath blocks for non-normalized Knuth-Yao (KY) sampling, as well as for the interpolation of non-linear functions (e.g., logarithmic, exponential), and (ii) direct data access to the register file of each neighboring core, to reduce the data movement costs of frequent data exchanges between nearby cores. To further capitalize on the parallelism potential in MCMC algorithms, we developed a specialized compile chain that enables efficient spatial mapping and scheduling across the cores.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 0 minor

Summary. The manuscript describes AIA, a multi-core RISC-V SoC fabricated in Intel 16 nm technology. It consists of a host RISC-V processor managing chip-to-chip communication and a 2D mesh of 16 custom versatile RISC-V cores. Each core includes custom instructions and datapath blocks for non-normalized Knuth-Yao sampling and non-linear function interpolation (e.g., log, exp), plus direct register-file access to neighboring cores to reduce data movement. A specialized compiler chain is provided to enable spatial mapping and scheduling of MCMC workloads for approximate inference on edge devices.

Significance. If the described custom instructions, neighbor register access, and compiler deliver the promised reductions in data movement and compute cost for MCMC workloads on the fabricated silicon, the work would constitute a meaningful contribution to domain-specific hardware for probabilistic inference. The 16 nm fabrication and explicit focus on discrete sampling workloads are concrete strengths that distinguish it from purely simulated architecture proposals.

major comments (1)
  1. [Abstract] Abstract: the central claim that the architecture is 'optimized for high-efficiency approximate inference' and will 'empower edge devices with robust decision-making' rests on unverified performance, power, and area benefits. The provided text contains no post-silicon measurements, cycle counts, energy figures, area overheads, or workload speedups relative to any baseline, rendering the efficiency assertions unevaluable.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for highlighting this issue with the abstract. We agree the claims require qualification given the content of the manuscript.

read point-by-point responses

  1. Referee: [Abstract] Abstract: the central claim that the architecture is 'optimized for high-efficiency approximate inference' and will 'empower edge devices with robust decision-making' rests on unverified performance, power, and area benefits. The provided text contains no post-silicon measurements, cycle counts, energy figures, area overheads, or workload speedups relative to any baseline, rendering the efficiency assertions unevaluable.

    Authors: We agree the abstract makes efficiency claims that are not supported by any quantitative results (post-silicon or otherwise) in the manuscript. The work presents the architecture, custom instructions, neighbor-register access, compiler, and 16 nm fabrication but contains no measured or simulated performance, power, or area data relative to baselines. We will revise the abstract to describe the design intent and features without asserting verified efficiency gains or edge-device empowerment. revision: yes

Circularity Check

0 steps flagged

No circularity: pure architecture description

full rationale

The paper presents a hardware SoC design, custom RISC-V instructions for sampling, and a mesh topology with no equations, fitted parameters, predictions, or derivation chain. All claims are descriptive of the fabricated design and compiler; no step reduces to its own inputs by construction or self-citation. The contribution is self-contained as an engineering artifact description.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

Hardware architecture paper; the only background premise is the well-known difficulty of parallelizing MCMC on general-purpose platforms.

axioms (1)
  • domain assumption MCMC methods come with significant computational costs and are inherently challenging to parallelize on conventional CPU/GPU platforms.
    Opening sentence of the abstract; used to motivate the need for the custom SoC.

pith-pipeline@v0.9.1-grok · 5798 in / 1236 out tokens · 61116 ms · 2026-06-27T03:00:02.656188+00:00 · methodology

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Reference graph

Works this paper leans on

47 extracted references · 3 canonical work pages

  1. [1]

    Thinking, fast and slow,

    D. Kahneman, “Thinking, fast and slow,”Farrar, Straus and Giroux, 2011

    2011

  2. [2]

    Neuro-symbolic= neural + logical + probabilistic,

    L. De Raedt, R. Manhaeve, S. Dumancic, T. Demeester, and A. Kimmig, “Neuro-symbolic= neural + logical + probabilistic,” inNeSy@ IJCAI, 2019

    2019

  3. [3]

    A survey on Bayesian deep learning,

    H. Wanget al., “A survey on Bayesian deep learning,”CSUR, 2020

    2020

  4. [4]

    C. C. Aggarwalet al.,Neural networks and deep learning. Springer, 2018, vol. 10, no. 978

    2018

  5. [5]

    Towards efficient neuro-symbolic ai: From workload characterization to hardware architecture,

    Z. Wan, C.-K. Liu, H. Yang, R. Raj, C. Li, H. You, Y . Fu, C. Wan, S. Li, Y . Kim, A. Samajdar, Y . Lin, M. Ibrahim, J. M. Rabaey, T. Krishna, and A. Raychowdhury, “Towards efficient neuro-symbolic ai: From workload characterization to hardware architecture,”IEEE Transactions on Circuits and Systems for Artificial Intelligence, vol. 1, no. 1, pp. 53–68, 2024

    2024

  6. [6]

    agrum/pyagrum: a toolbox to build models and algorithms for probabilistic graphical models in python

    G. Ducampet al., “agrum/pyagrum: a toolbox to build models and algorithms for probabilistic graphical models in python.” PMLR, 2020

    2020

  7. [7]

    Pyro: Deep universal probabilistic programming,

    E. Bingham, J. P. Chen, M. Jankowiak, F. Obermeyer, N. Pradhan, T. Karaletsos, R. Singh, P. Szerlip, P. Horsfall, and N. D. Goodman, “Pyro: Deep universal probabilistic programming,”Journal of machine learning research, vol. 20, no. 28, pp. 1–6, 2019

    2019

  8. [8]

    Turing: A language for flexible probabilistic inference,

    H. Ge, K. Xu, and Z. Ghahramani, “Turing: A language for flexible probabilistic inference,” inProceedings of the Twenty-First International Conference on Artificial Intelligence and Statistics, ser. Proceedings of Machine Learning Research, A. Storkey and F. Perez-Cruz, Eds., vol. 84. PMLR, 09–11 Apr 2018, pp. 1682–1690. [Online]. Available: https://proce...

    2018

  9. [9]

    Gen: A general-purpose probabilistic programming system with programmable inference,

    M. F. Cusumano-Towner, F. A. Saad, A. K. Lew, and V . K. Mans- inghka, “Gen: A general-purpose probabilistic programming system with programmable inference,” inProceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation, ser. PLDI 2019. ACM, 2019

    2019

  10. [10]

    Probabilistic reasoning in generative large language models,

    A. Nafar, K. B. Venable, and P. Kordjamshidi, “Probabilistic reasoning in generative large language models,”arXiv preprint arXiv:2402.09614, 2024

    work page arXiv 2024

  11. [11]

    Bird: A trustworthy bayesian inference framework for large language models,

    Y . Feng, B. Zhou, W. Lin, and D. Roth, “Bird: A trustworthy bayesian inference framework for large language models,”arXiv preprint arXiv:2404.12494, 2024

    work page arXiv 2024

  12. [12]

    3dp3: 3d scene perception via probabilistic programming,

    N. Gothoskaret al., “3dp3: 3d scene perception via probabilistic programming,”NIPS, 2021

    2021

  13. [13]

    A 16-nm soc for noise-robust speech and nlp edge ai inference,

    T. Tambeet al., “A 16-nm soc for noise-robust speech and nlp edge ai inference,”JSSC, 2022

    2022

  14. [14]

    Diana: An end- to-end energy-efficient digital and analog hybrid neural network soc,

    K. Ueyoshi, I. A. Papistas, P. Houshmand, G. M. Sarda, V . Jain, M. Shi, Q. Zheng, S. Giraldo, P. Vrancx, J. Doevenspecket al., “Diana: An end- to-end energy-efficient digital and analog hybrid neural network soc,” in2022 IEEE International Solid-State Circuits Conference (ISSCC), vol. 65. IEEE, 2022, pp. 1–3

    2022

  15. [15]

    Population-Based MCMC on Multi-Core CPUs, GPUs and FPGAs,

    G. Mingaset al., “Population-Based MCMC on Multi-Core CPUs, GPUs and FPGAs,”IEEE Transactions on Computers, 2016

    2016

  16. [17]

    Statheros: Compiler for efficient low-precision proba- bilistic programming,

    J. Laurelet al., “Statheros: Compiler for efficient low-precision proba- bilistic programming,” inDAC, 2021

    2021

  17. [18]

    The design process for google’s training chips: Tpuv2 and tpuv3,

    T. Norrie, N. Patil, D. H. Yoon, G. Kurian, S. Li, J. Laudon, C. Young, N. Jouppi, and D. Patterson, “The design process for google’s training chips: Tpuv2 and tpuv3,”IEEE Micro, vol. 41, no. 2, pp. 56–63, 2021

    2021

  18. [19]

    Dpu: Dag processing unit for irregular graphs with precision-scalable posit arithmetic in 28 nm,

    N. Shahet al., “Dpu: Dag processing unit for irregular graphs with precision-scalable posit arithmetic in 28 nm,”JSSC, 2021

    2021

  19. [20]

    Koller and N

    D. Koller and N. Friedman,Probabilistic graphical models: principles and techniques. MIT press, 2009

    2009

  20. [21]

    An introduction to mcmc for machine learning,

    C. Andrieu, N. De Freitas, A. Doucet, and M. I. Jordan, “An introduction to mcmc for machine learning,”Machine learning, vol. 50, pp. 5–43, 2003

    2003

  21. [22]

    Markov network structure learning: A randomized feature generation approach,

    J. Van Haaren and J. Davis, “Markov network structure learning: A randomized feature generation approach,” inProceedings of the AAAI Conference on Artificial Intelligence, vol. 26, no. 1, 2012, pp. 1148– 1154

    2012

  22. [23]

    An introduction to restricted boltzmann ma- chines,

    A. Fischer and C. Igel, “An introduction to restricted boltzmann ma- chines,” inProgress in Pattern Recognition, Image Analysis, Com- puter Vision, and Applications: 17th Iberoamerican Congress, CIARP 2012, Buenos Aires, Argentina, September 3-6, 2012. Proceedings 17. Springer, 2012, pp. 14–36

    2012

  23. [24]

    Coopmc: Algorithm-architecture co-optimization for markov chain monte carlo accelerators,

    Y . Chaiet al., “Coopmc: Algorithm-architecture co-optimization for markov chain monte carlo accelerators,” in2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2022

    2022

  24. [25]

    Demystifying bayesian inference workloads,

    Y . Emma Wang, Y . Zhu, G. G. Ko, B. Reagen, G.-Y . Wei, and D. Brooks, “Demystifying bayesian inference workloads,” in2019 IEEE Interna- tional Symposium on Performance Analysis of Systems and Software (ISPASS), 2019, pp. 177–189

    2019

  25. [26]

    Probabilistic machine learning and artificial intelli- gence,

    Z. Ghahramani, “Probabilistic machine learning and artificial intelli- gence,”Nature, vol. 521, no. 7553, pp. 452–459, 2015

    2015

  26. [27]

    Symbolic variable elimination for dis- crete and continuous graphical models,

    S. Sanner and E. Abbasnejad, “Symbolic variable elimination for dis- crete and continuous graphical models,” inProceedings of the AAAI Conference on Artificial Intelligence, vol. 26, no. 1, 2012, pp. 1954– 1960

    2012

  27. [28]

    Scaling exact inference for discrete probabilistic programs,

    S. Holtzen, G. Van den Broeck, and T. Millstein, “Scaling exact inference for discrete probabilistic programs,”Proceedings of the ACM on Programming Languages, vol. 4, no. OOPSLA, pp. 1–31, 2020

    2020

  28. [29]

    Graphical models: Probabilistic inference,

    M. I. Jordan and Y . Weiss, “Graphical models: Probabilistic inference,” The handbook of brain theory and neural networks, pp. 490–496, 2002

    2002

  29. [30]

    The emperor’s new markov blankets,

    J. Bruineberg, K. Dolkega, J. Dewhurst, and M. Baltieri, “The emperor’s new markov blankets,”Behavioral and Brain Sciences, vol. 45, p. e183, 2022

    2022

  30. [31]

    Performance analysis with cache-aware roofline model in intel advisor,

    D. Marques, H. Duarte, A. Ilic, L. Sousa, R. Belenov, P. Thierry, and Z. A. Matveev, “Performance analysis with cache-aware roofline model in intel advisor,” inHPCS. IEEE, 2017, pp. 898–907

    2017

  31. [32]

    Acmc 2: Accelerating markov chain monte carlo algorithms for probabilistic models,

    S. S. Banerjeeet al., “Acmc 2: Accelerating markov chain monte carlo algorithms for probabilistic models,” inProceedings of the Twenty- Fourth International Conference on Architectural Support for Program- ming Languages and Operating Systems, 2019

    2019

  32. [33]

    Mr.wolf: An energy-precision scalable parallel ultra low power soc for iot edge processing,

    A. Pulliniet al., “Mr.wolf: An energy-precision scalable parallel ultra low power soc for iot edge processing,”JSSC, 2019

    2019

  33. [34]

    Conti, G

    F. Conti, G. Paulin, A. Garofalo, D. Rossi, A. Di Mauro, G. Rutishauser, G. Ottavi, M. Eggiman, H. Okuhara, and L. Benini, “Marsellus: A heterogeneous risc-v ai-iot end-node soc with 2–8 b dnn acceleration and 30

  34. [35]

    Bayeslib,

    P. Dabbeltet al., “Bayeslib,” https://github.com/pulp-platform/ pulp-riscv-gnu-toolchain, 2023, online; accessed 2023-07-03

    2023

  35. [36]

    The fast loaded dice roller: A near-optimal exact sampler for discrete probability distributions

    F. Saadet al., “The fast loaded dice roller: A near-optimal exact sampler for discrete probability distributions.” PMLR, 2020

    2020

  36. [37]

    Constant-time discrete gaussian sampling,

    A. Karmakar, S. S. Roy, O. Reparaz, F. Vercauteren, and I. Verbauwhede, “Constant-time discrete gaussian sampling,”IEEE Transactions on Com- puters, vol. 67, no. 11, pp. 1561–1571, 2018

    2018

  37. [38]

    High precision discrete gaussian sampling on fpgas,

    S. Sinha Roy, F. Vercauteren, and I. Verbauwhede, “High precision discrete gaussian sampling on fpgas,” inInternational Conference on Selected Areas in Cryptography. Springer, 2013, pp. 383–401

    2013

  38. [39]

    Discrete samplers for approximate inference in proba- bilistic machine learning,

    S. Zhaoet al., “Discrete samplers for approximate inference in proba- bilistic machine learning,” inDATE, 2022

    2022

  39. [40]

    A review of bayesian networks and structure learning,

    T. J. Koski and J. Noble, “A review of bayesian networks and structure learning,”Mathematica Applicanda, vol. 40, no. 1, 2012

    2012

  40. [41]

    Accelerating markov random field inference with uncertainty quantification,

    R. Bashizadeet al., “Accelerating markov random field inference with uncertainty quantification,”arXiv:2108.00570, 2021

    work page arXiv 2021

  41. [42]

    Bayesian networks for supply chain risk, resilience and ripple effect analysis,

    S. Hosseiniet al., “Bayesian networks for supply chain risk, resilience and ripple effect analysis,”Expert systems with applications, 2020

    2020

  42. [43]

    Bayesian networks for risk prediction using real-world data: a tool for precision medicine,

    P. Aroraet al., “Bayesian networks for risk prediction using real-world data: a tool for precision medicine,”Value in Health, 2019

    2019

  43. [44]

    A performance comparison of graph coloring algorithms,

    M. Aslan and N. A. Baykan, “A performance comparison of graph coloring algorithms,”International Journal of Intelligent Systems and Applications in Engineering, vol. 4, no. Special Issue-1, pp. 1–7, 2016

    2016

  44. [45]

    Hammer: a modular and reusable physical design flow tool,

    H. Liew, D. Grubb, J. Wright, C. Schmidt, N. Krzysztofowicz, A. Izraelevitz, E. Wang, K. Asanovi ´c, J. Bachrach, and B. Nikoli ´c, “Hammer: a modular and reusable physical design flow tool,” inPro- ceedings of the 59th ACM/IEEE Design Automation Conference, 2022, pp. 1335–1338

    2022

  45. [46]

    Bayesian networks for interpretable machine learning and optimization,

    B. Mihaljevi ´cet al., “Bayesian networks for interpretable machine learning and optimization,”Neurocomputing, 2021

    2021

  46. [47]

    Statistical robustness of markov chain monte carlo accelerators,

    X. Zhang, R. Bashizade, Y . Wang, S. Mukherjee, and A. R. Lebeck, “Statistical robustness of markov chain monte carlo accelerators,” in Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021, pp. 959–974

    2021

  47. [48]

    Bayeslib,

    M. Pronesti, “Bayeslib,” https://github.com/mspronesti/baylib, 2024, on- line; accessed 2024-07-03

    2024